843023AG

www.icst.com/products/hiperclocks.html

REV. A NOVEMBER 30, 2004

5

Integrated

Circuit

Systems, Inc.

ICS843023

PRELIMINARY

The ICS843023 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 1 below were determined using a 25MHz, 18pF parallel

resonant crystal and were chosen to minimize the ppm error.

The optimum C1 and C2 values can be slightly adjusted for

different board layouts.

C1

33p

X1

18pF Parallel Crystal

C2

27p

XTAL_OUT

XTAL_IN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

drive 50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion.

Figures 2A and 2B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

(V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN