Timing Solutions

Freescale Semiconductor

3

MPC9855

Table 1. Pin Configurations

Pin

I/O

Type

Function

Supply

Active/State

CLK

Input

LVCMOS PLL reference clock input (pull-down)

—

PCLK, PCLK

Input

LVPECL PLL reference clock input

(PCLK — pull-down, PCLK — pull-up and pull-down)

—

QA0, QA1,

QA2, QA3

QB0, QB1,

QB2, QB3

Output

LVCMOS Clock Outputs

—

REF_OUT0

REF_OUT1

Output

LVCMOS Reference Output (25 MHz or 33 MHz)

—

XTAL_IN

Input

LVCMOS Crystal Oscillator Input Pin

—

XTAL_OUT

Output

LVCMOS Crystal Oscillator Output Pin

—

CLK_SEL

Input

LVCMOS Select between CLK and PCLK input (pull-down)

High

XTAL_SEL

Input

LVCMOS Select between External Input and Crystal Oscillator Input

(pull-down)

High

REF_33 MHz

Input

LVCMOS Selects 33MHz input (pull-down)

High

REF_OUT1_E

Input

LVCMOS Enables REF_OUT! output (pull-down)

High

MR

Input

LVCMOS Master Reset (pull-up)

Low

PLL_BYPASS

Input

LVCMOS Select PLL or static test mode (pull-up)

High

1. Power PC bit ordering (bit 0 = msb, bit 5 = lsb).

Input

LVCMOS Configures Bank A clock output frequency (pull-up)

—

Input

LVCMOS Configures Bank B clock output frequency (pull-up)

—

—

—

3.3 V Supply

—

—

—

—

Analog Supply

—

—

—

—

Output Supply — Bank A

—

—

—

—

Output Supply — Bank B

—

—

GND

—

—

Ground

—

—

Table 2. Function Table

Control

Default

0

1

CLK_SEL

0

CLK

PCLK

XTAL_SEL

0

CLKx

XTAL

PLL_BYPASS

0

Normal

Bypass

REF_OUT1_E

0

Disables REF_OUT1

Enables REF_OUT1

REF_33 MHz

0

Selects 25 MHz Reference

Selects 33 MHz Reference

MR

1

Reset

Normal

CLK_A and CLK_B control output frequencies. Refer to Table 3 for specific device configuration