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COP8TAB9 Datasheet(PDF) 22 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # COP8TAB9
Description  8-Bit CMOS Flash Microcontroller with 2k Byte or 4k Byte Memory
PDF  59 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP8TAB9 Datasheet(HTML) 22 Page - National Semiconductor (TI)

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11.0 In-System Programming
(Continued)
should be placed into the address registers of COP8TAC9
devices. Registers ISPADHI and ISPADLO are cleared to 00
on Reset.
Note: The actual memory address of the Option Register is
0x0FFF (hex), however the MICROWIRE/PLUS ISP routines
require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
TABLE 6. High Byte of ISP Address
ISPADHi
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr 15
Addr 14
Addr 13
Addr 12
Addr 11
Addr 10
Addr 9
Addr 8
TABLE 7. Low Byte of ISP Address
ISPADLO
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr 7
Addr 6
Addr 5
Addr 4
Addr 3
Addr 2
Addr 1
Addr 0
11.3.2 ISP Read Data Register
The Read Data Register (ISPRD) contains the value read
back from a read operation. This register is undefined on
Reset.
TABLE 8. ISP Read Data Register
ISPRD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
11.3.3 ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be
written into the specified address. This register is undeter-
mined on Reset.
TABLE 9. ISP Write Data Register
ISPWR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
11.3.4 ISP Write Timing Register
The Write Timing Register (PGMTIM) is used to control the
width of the timing pulses for write and erase operations. The
value to be written into this register is dependent on the
frequency of CKI and is shown in Table 10. This register
must be written before any write or erase operation can take
place. It only needs to be loaded once, for each value of CKI
frequency. The MICROWIRE/PLUS ISP routine that is resi-
dent in the boot ROM requires that this register be defined
prior to any access to the Flash memory. Refer to Section
11.7 MICROWIRE/PLUS ISP for more information on avail-
able ISP commands. On Reset, the PGMTIM register is
loaded with the value that corresponds to 10 MHz frequency
for CKI. The best choice for value of PGMTIM will center the
operating frequency in the CKI Frequency Range.
TABLE 10. PGMTIM Register Format
PGMTIM
Register Bit
CKI Frequency Range
7
654
32
1
0
0
0
0
0
0
0
0
0
25 kHz–50 kHz
0
0
0
0
0
0
0
1
50 kHz–100 kHz
0
0
0
0
0
0
1
0
75 kHz–150 kHz
0
0
0
0
0
1
0
0
125 kHz–250 kHz
0
0
0
0
0
1
1
1
200 kHz–400 kHz
0
0
0
0
1
0
1
0
275 kHz–550 kHz
0
0
0
1
0
0
0
0
425 kHz–850 kHz
0
0
0
1
1
0
0
0
625 kHz–1.25 MHz
0
0
1
0
1
0
0
0
1.025 MHz–2.05 MHz
0
1
0
0
0
1
0
1
1.5 MHz–3 MHz
0
1
0
0
1
0
0
1
2.5 MHz–5 MHz
0
1
0
0
1
1
1
0
3.75 MHz–7.5 MHz
0
1
0
1
1
0
1
0
6.75 MHz–13.5 MHz
0
1
1
0
1
1
0
0
11.25 MHz–22.5 MHz
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
www.national.com
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