ES4228 datasheet(4/8 Pages) ETC

4 / 8 page

SAM0378-053001

ESS Technology, Inc.

ES4228/ES4227 PRODUCT BRIEF

Name

Number

I/O

Description

DMA[11:0]

66:61, 58:53

DRAM address bus.

DCAS#

DRAM column address strobe.

DOE#

DRAM output enable.

DSCK_EN

DRAM system clock enable.

DWE#

DRAM write enable.

DRAS[2:0]#

74:72

DRAM row address strobe.

DB[15:0]

96:93, 90:85 ,82:77

I/O

DRAM data bus.

DCS[1:0]#

97, 100

SDRAM chip select [1:0].

DQM

101

Data input/output mask.

DSCK

102

DRAM system clock to SDRAM.

DCLK

105

Clock input (bypass/test mode).

YUV[7:0]

115:113, 110:106

8-bit YUV output.

PCLK2XSCN

116

I/O

2X pixel clock.

PCLKQSCN

117

I/O

Pixel clock.

VSYNC#

118

I/O

Vertical sync.

HSYNC#

119

I/O

Horizontal sync.

HD[15:0]

141:140, 137:131, 128:122

I/O

Host data bus

VPP

159

5 V power supply.

AUX[7:0]

169:165, 162:160

I/O

Auxiliary ports.

LOE#

170

EPROM device output enable.

LCS[3:0]#

176:173

EPROM chip select [3:0].

LD[15:0]

197:194,191:185,182:178

I/O

EPROM device data bus.

LWRLL#

198

EPROM device low byte write enable.

LWRHL#

199

EPROM device high byte write enable.

37, 38, 41, 42, 146:142,

155:149, 158, 203:202

—

No connect.

Table 1

ES4228 Pin Descriptions List (Continued)

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