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TAS5755MDFDR Datasheet(PDF) 21 Page - Texas Instruments |
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TAS5755MDFDR Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 76 page  MCLK SCLK LRCLK Protection Logic Click and Pop Control Digital Audio Processor (DAP) SDA SCL 4 -Order th Noise Shaper and PWM S R C Sample Rate Autodetect and PLL Serial Control Microcontroller Based System Control Terminal Control OUT_A OUT_B 2 HB ´ FET Out OUT_C OUT_D 2 HB ´ FET Out B0262-14 SDIN Serial Audio Port 21 TAS5755M www.ti.com SLOS982 – AUGUST 2017 Product Folder Links: TAS5755M Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8 Parameter Measurement Information All parameters are measured according to the conditions described in the Specifications section. 9 Detailed Description 9.1 Overview The TAS5755M an efficient 50-W stereo I2S input Class-D audio power amplifier. The digital auto processor of the device uses noise shaping and customized correction algorithms to achieve a great power efficiency and high audio performance. Also, the device has up to eight Equalizers per channel and two -band configurable Dynamic Range Control (DRC). The device needs only a single DVDD supply in addition to the higher-voltage PVDD power supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuit. The wide PVDD power supply range of the device enables its use in a multitude of applications. The TAS5755M is a slave-only device that is controlled by a bidirectional I2C interface that supports both 100- kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This control interface is used to program the registers of the device and read the device status. The PWM of this device operates with a carrier frequency between 384 kHz and 354 kHz, depending the sampling rate. This device allows the use of the same clock signal for both MCLK and BCLK (64xFs) when using a sampling frequency of 44.1 kHz or 48 kHz. This device can be used in three different modes of operation, Stereo BTL mode, Single filter PBTL mono mode, and 2.1 mode. 9.2 Functional Block Diagrams Figure 43. Functional Block Diagram |
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