AD4001 datasheet(21/37 Pages) AD

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Data Sheet

AD4001/AD4005

Rev. B | Page 21 of 37

the device by clamping the input voltage in a safe operating

range and avoiding disturbance of the reference, which is

particularly important for systems that share the reference

among multiple ADCs.

If the analog input exceeds the reference voltage by 0.4 V, the

internal clamp circuit turns on and the current flows through

the clamp into ground, preventing the input from rising further

and potentially causing damage to the device. The clamp turns

on before D1 (see Figure 36) and can sink up to 50 mA of current.

When the clamp is active, it sets the OV clamp flag bit in the

that must be read to be cleared. The status of the clamp can also

be checked in the status bits using an overvoltage clamp flag

(see Table 15). The clamp circuit does not dissipate static power

in the off state. Note that the clamp cannot sustain the overvoltage

condition for an indefinite amount of time.

The external RC filter is usually present at the ADC input to

band limit the input signal. During an overvoltage event, excessive

voltage is dropped across REXT, and REXT becomes part of a

protection circuit. The REXT value can vary from 200 Ω to 20 kΩ

for 15 V protection. The CEXT value can be as low as 100 pF for

correct operation of the clamp. See Table 1 for input overvoltage

clamp specifications.

Differential Input Considerations

The analog input structure allows the sampling of the true

differential signal between IN+ and IN−. By using these differential

inputs, signals common to both inputs are rejected. Figure 37

shows the common-mode rejection capability of the AD4001/

AD4005 over frequency. It is important to note that the differential

input signals must be truly antiphase in nature, 180° out of phase,

which is required to keep the common-mode voltage of the input

signal within the specified range around VREF/2 as shown in Table 1.

100

10k

100k

FREQUENCY (Hz)

Figure 37. CMRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C

Switched Capacitor Input

During the acquisition phase, the impedance of the analog

inputs (IN+ or IN−) can be modeled as a parallel combination

of Capacitor CPIN and the network formed by the series connection

of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically

400 Ω and is a lumped component composed of serial resistors

and the on resistance of the switches. CIN is typically 40 pF and

is mainly the ADC sampling capacitor.

During the conversion phase, where the switches are open, the

input impedance is limited to CPIN. RIN and CIN make a single-

pole, low-pass filter that reduces undesirable aliasing effects and

limits noise.

RC Filter Values

The RC filter value (represented by R and C in Figure 32 to

Figure 35) and driving amplifier can be selected depending on

the input signal bandwidth of interest at the full throughput.

Lower input signal bandwidth means that the RC cutoff can be

lower, thereby reducing noise into the converter. For optimum

performance at various throughputs, use the recommended RC

values (200 Ω, 180 pF) and the ADA4807-1.

The RC values shown in Table 10 are chosen for ease of

drive considerations and greater ADC input protection. The

combination of a large R value (200 Ω) and small C value

results in a reduced dynamic load for the amplifier to drive. The

smaller value of C means fewer stability and phase margin

concerns with the amplifier. The large value of R limits the current

into the ADC input when the amplifier output exceeds the ADC

input range.

Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths

Input Signal Bandwidth (kHz)

R (Ω)

C (pF)

Recommended Amplifier

Recommended Fully Differential Amplifier

<10

See the High-Z Mode section

ADA4940-1

<200

200

180

ADA4807-1

ADA4940-1

>200

200

120

ADA4897-1

ADA4932-1

Multiplexed

200

120

ADA4897-1

ADA4932-1

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