AD7616-P datasheet(28/47 Pages) AD

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Data Sheet

AD7616-P

Rev. 0 | Page 27 of 46

DIGITAL INTERFACE

CHANNEL SELECTION

Hardware Mode

The logic level of the CHSELx signals determines the channel

pair for conversion; see Table 12 for signal decoding information.

The CHSELx signals at the time that either full or partial reset is

released determine the initial channel pair to sample. After a reset,

the logic levels of the CHSELx signals are examined during the

BUSY high period to set the channel pair for the next conversion.

The CHSELx signal level must be set before CONVST goes from

low to high and must be maintained until BUSY goes from high

to low to indicate a conversion is complete. See Figure 49 for

further details.

Software Mode

In software mode, the channels for conversion are selected

using the channel register. On power-up or after a reset, the

default channels selected for conversion are Analog Input V0A

and Analog Input V0B.

Table 12. CHSELx Pin Decoding

Channel Selection Input Pin

Analog Inputs for Conversion

CHSEL0

CHSEL1

CHSEL2

V0A, V0B

V1A, V1B

V2A, V2B

V3A, V3B

V4A, V4B

V5A, V5B

V6A, V6B

V7A, V7B

Figure 49. Hardware Mode Channel Conversion Setting

Figure 50. Software Mode Channel Conversion Setting

RESET

CONVST

BUSY

CHX

A/BX

A/BY

A/BZ

CHY

CHZ

CH...

CHSEL2

CHSEL0

DATA BUS

CONFIGURE POINT

INITIAL SETUP

RESET

CONVST

BUSY

CHX

B0 CHY

BX CHZ

BY CH

DB0 TO

DB15

CHx CONVERSION START

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