AD7616-PBSTZ datasheet(32/47 Pages) AD

32 / 47 page

Data Sheet

AD7616-P

Rev. 0 | Page 31 of 46

Figure 55. Software Mode Sequencer Configuration

To configure and enable the sequencer, it is recommended to

complete the following procedure (see Figure 55):

1. Configure the analog input range for the required analog

input channels.

2. Program the sequencer stack registers to select the

channels for the sequence.

3. Set the SSRENx bit in the last required sequence step.

4. Set the SEQEN bit in the configuration register.

5. Provide a dummy CONVST pulse.

6. Cycle through CONVST pulses and conversion reads to step

through each element of the sequencer stack.

The sequence automatically restarts from the first element in

the sequencer stack with the next CONVST pulse.

Following a partial reset, the sequencer pointer is repositioned

to the first layer of the stack, but the register programmed

values remain unchanged.

BURST SEQUENCER

Burst mode avoids generating a CONVST pulse for each step in

a sequence of conversions. One CONVST pulse converts every

step in the sequence.

The burst sequencer is an additional feature that works in

conjunction with the sequencer. If the burst function is enabled,

one CONVST pulse initiates a conversion of all the channels

configured in the sequencer. The burst function avoids generating

a CONVST pulse for each step in a sequence of conversions, as

is the case when the burst function is disabled.

Configuration of the burst function varies depending on the

mode of operation: hardware or software mode. See the Hardware

Mode Burst section and the Software Mode Burst section for

specific details on configuring the burst function in each mode.

When configured, the burst sequence is initiated at the rising

edge of CONVST. The BUSY pin goes high to indicate that a

conversion is in progress. The BUSY pin remain highs until all

conversions in the sequence are complete. The conversion

results are available for readback after the BUSY pin goes low.

The number of data reads required to read all the data in the burst

sequence is dependent on the length of the sequence configured.

The conversion results are presented on the parallel data bus in

the same order as the programmed sequence.

The throughput rate of the AD7616-P is limited in burst mode

and dependent on the length of the sequence. Each channel pair

requires an acquisition, conversion, and readback time. The

time taken to complete a sequence with number of channel

pairs, N, is estimated by

tBURST = (tCONV + 25 ns) + (N – 1)(tACQ + tCONV) + N(tRB)

where:

tCONV is the typical conversion time.

tACQ is typical acquisition time.

tRB is the time required to read back the conversion results.

Hardware Mode Burst

Burst mode is enabled in hardware mode by setting the WR/

BURST pin to 1. The SEQEN pin must also be set to 1 to enable the

sequencer.

In hardware mode, the burst sequencer is controlled by the BURST,

SEQEN, and CHSELx pins. The burst sequencer is enabled or

disabled when the AD7616-P is released from full reset. The

logic level of the SEQEN pin and the BURST pin when

the RESET pin is released determines whether the burst

sequencer is enabled or disabled. After the RESET pin is

released, the burst sequencer function is fixed and a full reset

via the RESET pin is required to exit the function and set up an

alternative configuration.

When the burst sequencer is enabled, the logic levels of the

CHSELx pins determine the channels selected for conversion in the

burst sequence. The CHSELx pins at the time RESET is released

determine the initial settings for the channels to convert in the

burst sequence. To reconfigure the channels selected for conver-

sion after a reset, set the CHSELx pins to the required setting

for the duration of the next BUSY pulse (see Figure 56 for

further details).

Software Mode Burst

In software mode, the burst function is enabled by setting the

BURSTEN bit in the configuration register to 1. This action

must be performed when setting the SEQEN bit in the

configuration register as outlined in the steps described in the

Software Mode Sequencer section to configure the sequencer

(see Figure 57 for additional information).

RESET

CONVST

BUSY

SETUP

A/B0

Sn – 1

DATA

INITIAL SETUP

SEQUENCE START

DUMMY CONVERSION

SEQUENCE START

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