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EVAL-AD7902SDZ Datasheet(PDF) 24 Page - Analog Devices |
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EVAL-AD7902SDZ Datasheet(HTML) 24 Page - Analog Devices |
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24 / 29 page ![]() Data Sheet AD7902 Rev. B | Page 23 of 28 Chain Mode with Busy Indicator Chain mode with a busy indicator can also be used to daisy- chain both ADCs within an AD7902 on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with limited interfacing capacity. Data readback is analogous to clocking a shift register. See Figure 48 for a connection diagram example using three AD7902 ADCs. The corresponding timing is shown in Figure 49. When SDIx and CNVx are low, SDOx is driven low. With SCKx high, a rising edge on CNVx initiates a conversion, selects chain mode, and enables the busy indicator feature. In this mode, CNVx is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the SDOx pin of the ADC closest to the digital host (see the ADC labeled ADCx in the AD7902 B box in Figure 48) is driven high. This transition on SDOx can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7902 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCKx falling edges. For each ADC, SDIx feeds the input of the internal shift register and is clocked by the SCKx falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCKx falling edge allows a faster reading rate and, consequently, more ADCs in the chain, provided that the digital host has an acceptable hold time. Figure 48. Chain Mode with a Busy Indicator Connection Diagram Figure 49. Chain Mode with a Busy Indicator Serial Interface Timing CONVERT DATA IN CLK DIGITAL HOST AD7902 SDIxB SDOxB CNVx SCKx AD7902 AD7902 A AD7902 B SDI1A SDO1A CNVx SCKx IRQ AD7902 SDI2A SDO2A CNVx ADCx ADC1 ADC2 SCKx NOTES 1. DASHED LINE DENOTED ADCs ARE WITHIN A GIVEN PACKAGE. 2. SDI1A AND SDO1A REFER TO THE SDI1 AND SDO1 PINS IN ADC1 IN THE FIRST AD7902 OF THE CHAIN (AD7902 A). SDI2A AND SDO2A REFER TO THE SDI2 AND SDO2 PINS IN ADC2 OF AD7902 A. LIKEWISE, SDIxB AND SDOxB REFER TO THE SDIx AND SDOx PINS IN BOTH ADC1 AND ADC2 OF THE SECOND AD7902 IN THE CHAIN (AD7902 B). tCONV tCYC tSSDISCK tSCKH tSCK tHSDISCK tACQ tDSDOSDI tDSDOSDI tDSDODSI ACQUISITION tSSCKCNV ACQUISITION tSCKL CONVERSION tHSCKCNV SCKx CNVx = SDI1A SDO1A = SDI2A SDO2A = SDIxB SDOxB tEN DA115 DA114 DA113 DA215 DA214 DA213 DBx15 DBx14 DBx13 DA21 DA20 DA115 DA114 DA11 DA10 DBx1 DBx0 DA215 DA214 DA10 DA11 DA20 DA21 DA114 DA115 DA11 DA10 tHSDO 1 2 3 15 16 17 4 18 19 31 32 33 34 35 47 48 49 tDSDO tDSDOSDI tDSDOSDI |
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