AD9249-65EBZ datasheet(27/37 Pages) AD

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AD9249

Data Sheet

Rev. 0 | Page 26 of 36

SERIAL PORT INTERFACE (SPI)

The AD9249 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

offers the user added flexibility and customization, depending on

the application. Addresses are accessed via the serial port and

can be written to or read from via the port. Memory is organized

into bytes that can be further divided into fields, which are docu-

mented in the Memory Map section. For general operational

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI. SPI information specific to the AD9249

is found in the AD9249 datasheet and takes precedence over the

general information found in the AN-877 Application Note.

CONFIGURATION USING THE SPI

Four pins define the SPI of this ADC: the SCLK/DTP pin

(SCLK functionality), the SDIO/DFS pin(SDIO functionality),

and the CSB1 and CSB2 pins (see Table 15). SCLK (a serial

clock) is used to synchronize the read and write data presented

from and to the ADC. SDIO (serial data input/output) serves a

dual function that allows data to be sent to and read from the

internal ADC memory map registers. CSB1 and CSB2 (chip

select bar) are active low controls that enable or disable the read

and write cycles.

Table 15. Serial Port Interface Pins

Function

SCLK

(SCLK/DTP)

Serial clock. The serial shift clock input, which is

used to synchronize serial interface reads and

writes.

SDIO

(SDIO/DFS)

Serial data input/output. A dual-purpose pin that

serves as an input or an output, depending on the

instruction being sent and the relative position in

the timing frame.

CSB1,

CSB2

Chip select bar. An active low control that gates

the read and write cycles. CSB1 enables/disables

SPI for eight channels in Bank 1; CSB2 enables/

disables SPI for eight channels in Bank 2.

The falling edge of CSB1 and/or CSB2, in conjunction with the

rising edge of SCLK, determines the start of the framing. For an

example of the serial timing and its definitions, see Figure 50

and Table 5.

Other modes involving the CSB1 and CSB2 pins are available.

To permanently enable the device, hold CSB1 and CSB2 low

indefinitely; this is called streaming. CSB1 and CSB2 can stall

high between bytes to allow additional external timing. Tie CSB1

and CSB2 high to place SPI functions in high impedance mode.

This mode turns on any SPI secondary pin functions.

It is recommended that CSB1 and CSB2 be controlled with the

same signal by tying them together. In this way, whether tying

them to AVDD or selecting SPI functionality, both banks of ADCs

are controlled identically and are always in the same state.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to both program the chip and read the contents

of the on-chip memory. The first bit of the first byte in a multibyte

serial data transfer frame indicates whether a read command or a

write command is issued. If the instruction is a readback operation,

performing a readback causes the serial data input/output (SDIO)

pin to change direction from an input to an output at the

appropriate point in the serial frame.

Input data registers on the rising edge of SCLK, and output data

transmits on the falling edge. After the address information passes

to the converter requesting a read, the SDIO line transitions from

an input to an output within 1/2 of a clock cycle. This timing

ensures that when the falling edge of the next clock cycle

occurs, data can be safely placed on this serial line for the

controller to read.

All data is composed of 8-bit words. Data can be sent in MSB

first mode or in LSB-first mode. MSB-first mode is the default

on power-up and can be changed via the SPI port configuration

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI.

Figure 50. Serial Port Interface Timing Diagram

DON’T CARE

SDIO

SCLK

CSB1,

CSB2

tDH

tCLK

tDS

R/W

A12

A11

A10

tLOW

tHIGH

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