AD9689-2000EBZ datasheet(83/134 Pages) AD

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Data Sheet

AD9689

Rev. A | Page 83 of 134

DETERMINISTIC LATENCY

Both ends of the JESD204B link contain various clock domains

distributed throughout each system. Data traversing from one

clock domain to a different clock domain can lead to ambiguous

delays in the JESD204B link. These ambiguities lead to non-

repeatable latencies across the link from one power cycle or link

reset to the next. Section 6 of the JESD204B specification

addresses the issue of deterministic latency with mechanisms

defined as Subclass 1 and Subclass 2.

The AD9689 supports JESD204B Subclass 0 and Subclass 1

operation. Register 0x0590, Bits[7:5] set the subclass mode for the

AD9689 and its default is set for Subclass 1 operating mode

(Register 0x0590, Bit 5 = 1). If deterministic latency is not a

system requirement, Subclass 0 operation is recommended and

the SYSREF signal may not be required. Even in Subclass 0

mode, the SYSREF signal may be required in an application

where multiple AD9689 devices must be synchronized with

each other. This topic is addressed in the Timestamp Mode

section.

SUBCLASS 0 OPERATION

If there is no requirement for multichip synchronization while

operating in Subclass 0 mode (Register 0x0590, Bits[7:5] = 0

decimal), the SYSREF input can be left disconnected. In this mode,

the relationship of the JESD204B clocks between the JESD204B

transmitter and receiver are arbitrary, but does not affect the ability

of the receiver to capture and align the lanes within the link.

SUBCLASS 1 OPERATION

The JESD204B protocol organizes data samples into octets, frames,

and multiframes as described in the Transport Layer section.

The LMFC is synchronous with the beginnings of these

multiframes. In Subclass 1 operation, the SYSREF signal

synchronizes the LMFCs for each device in a link or across

multiple links (within the AD9689, SYSREF also synchronizes

the internal sample dividers), as shown in Figure 143. The

JESD204B receiver uses the multiframe boundaries and

buffering to achieve consistent latency across lanes (or even

multiple devices), and to achieve a fixed latency between power

cycles and link reset conditions.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic

latency in a JESD204B Subclass 1 system.

•

SYSREF± signal distribution skew within the system must

be less than the desired uncertainty for the system.

•

SYSREF± setup and hold time requirements must be met

for each device in the system.

•

The total latency variation across all lanes, links, and

devices must be ≤1 LMFC periods (see Figure 143). This

includes both variable delays and the variation in fixed

delays from lane to lane, link to link, and device to device

in the system.

SYSREF ALIGNED

GLOBAL LMFC

ALL LMFCs

DATA

DEVICE CLOCK

SYSREF

ILAS

DATA

SYSREF TO LMFC DELAY

POWER CYCLE VARIATION

(MUST BE <

tLMFC)

Figure 143. SYSREF and LMFC

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