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Preliminary Technical Data

AD6650

REV. PrJ 02/27/2003

SERIAL OUTPUT DATA PORT

The AD6650 has two configurable serial output ports (SDO0,

SDO1). Both ports must be configured the same and

programmed using the same control register. The ports also

share a common SFDS, SCLK, and DR pin for connection to an

external ASIC or DSP. As such, the outputs may be configured

as either serial master or serial slave, but cannot be programmed

independently.

Serial Output Data Format

The AD6650 utilizes a normal linear binary data format with

serial data frame word lengths of 16- or 24-bit precision. In this

mode, the data is shifted out of the device in Big Endian format

(MSB first).

Serial Data Frame Sync (Serial Bus Master)

The serial data frame is initiated with the Serial Data Frame

Sync (SDFS). As each channel within the AD6650 completes a

filter cycle, data is transferred into the serial data buffer. In the

Serial Bus Master (SBM) mode, the internal serial controller

initiates the SDFS on the next rising edge of the serial clock. In

the AD6650, there are 3 or 4 modes in which the frame sync

may be generated as a Serial Bus Master. In the case where both

A and B input channels are processed through SDO0 only, there

are four modes, and when A and B input channels are output

through SDO0 and SDO1 respectively, there are three modes of

operation (mode 0 and 1 are the same). These modes are

described in section SDFS Modes.

Serial Data Frame (Serial Cascade)

Any of the AD6650 serial outputs may be operated in the serial

cascade mode (serial slave). In this mode, the selected AD6650

channel requires that an external device such as a DSP to issue

the serial clock and SDFS.

To operate successfully in the serial cascade mode, the DSP

must have some indication that the AD6650 channel’s serial

buffer is ready to send data. This is indicated by the assertion of

the DR. This pin should be tied to an interrupt or flag pin of the

DSP. In this manner, the DSP will know when to service the

serial port.

When the DSP begins handling the serial service, the serial port

should be configured such that the SDFS pin is asserted one

clock cycle prior to shifting data. As such, the AD6650 channel

samples the SFDS pin on the rising edge of the serial clock. On

the next rising edge of the serial clock the AD6650 serial port

begins shifting data until the specified number of bits have been

shifted.

Configuring the Serial Ports

Both Serial Output Ports can either function as a Master or

Slave, but they cannot be set independently. A Serial Bus

Master will provide SCLK and SDFS outputs. Serial Ports 0 and

1 will always default to serial slaves when RESET is taken low,

but the Serial Ports can be programmed to become master by

setting the SBM bit in the serial control register high.

Serial Port Data Rate

If the Serial Ports are defined as a master, the SCLK frequency

is defined by Equation x. fCLK is the frequency of the master

clock of the AD6650 channel and SDIV is the Serial Division

word for the channel. The SDIV for Serial Port 0 and 1 can be

programmed via the internal control register 0x22.

Serial Slave Operation

The AD6650 can also be operated as a serial bus slave. In this

configuration, shown in Figure x, the serial clock provided by

the DSP can be asynchronous with the AD6650 clock and input

data In this mode the clock has a maximum frequency of 52

MHz and must be fast enough to read the entire serial frame

prior to the next frame coming available. The AD6650 output is

derived (via the Decimation/Interpolation Rates) from its input

sample rate, so the user can determine the output rate. The output

rate of the AD6650 is given below.

Serial Ports Cascaded

Serial output ports may be cascaded on the AD6650. This

allows data to be shifted out of the master and slave channel in

parallel. To accomplish this, the SDFS signal of the master

channel drives the SDFS input of the slave channel

Using the AD6650 master/slave mode permits a DSP to shift the

data from the master AD6650 serial port, in parallel with a frame

of data (I and Q words) from the AD6650 slave port. As shown

in Figure xx, the Master Port is Serial Port 0. The Slave Port is

Serial Port 0 and 1 from another AD6650. The only limit to the

number of ports that can be cascaded comes from serial

bandwidth and fan-out considerations.

There must be enough Serial Clock cycles available to shift the

necessary data into the DSP, and the SCLK (common to all

channels and DSP) must be closely monitored to ensure that it is

a clean signal.

Serial Output Frame Timing (Master and Slave)

The SDFS signal transitions accordingly depending on whether

the part is in Master (SBM = 1, Figure xx) or Slave (SBM = 0,

Figure xx) mode. The next rising edge of SCLK after this occurs

will drive the first bit of the serial data on the SDO pin. The

falling edge of SCLK or the subsequent rising edge can then be

used by the DSP to sample the data until the required number of

bits is received (determined by the serial output port word

length). If the DSP has the ability to count bits, the DSP will

know when the complete frame is received.

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