T0514TP datasheet(4/9 Pages) CITC

4 / 9 page

Application Information

Pin Connection in PCB

lines simultaneously. The pin connection is shown

in the ﬁgure below.

Four parallel data lines, from inner IC to I/O port

connector,

coule connect to T0514TP four I/O pins

directly. Pin 3&8 of T0514TP is the GND pin, which

should connect to the

GND of PCB. The wire should

be as short as possible in order to minimize the

parasitic inductance.

PCB Layout Guidelines

For optimum ESD protection and the whole circuit

performance, the following PCB layout guidelines are

recommended:

should be as short as possible. It could

reduce the

ESD transient return path to GND.

The vias connecting T0514TP GND pins to the

PCB GND should be wide

Place

possible. It could reduce the parasitic inductance

and restrict ESD coupling into adjacent traces.

Avoid running critical signals near board edges.

T0514TP GND pin to the PCB GND rail path

T0514TP as close to the connector port as

T0514TP provides ESD protection for four data

I/O1

I/O2

I/O4

I/O3

igure 1 T0514TP in connection in PCB

Ultra-Low Capacitance ESD Protection Device

T0514TP

Chip Integration Technology Corporation

GND

To I/O Port

Connector

Date lines

To I/O Port

Connector

Date lines

To Inner IC

Date lines

To Inner IC

Date lines

□

Document ID : DS-22V17

Revised Date : 2017/07/20

Revision : C

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