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CY29949
Document #: 38-07289 Rev. *D
Page 4 of 7
Notes:
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50
Ω transmission lines.
8. 50% input duty cycle.
9. See Figures 1 and 2.
10. Part-to-Part skew at a given temperature and voltage.
AC Parameters (VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range)
[6]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
Fmax
Input Frequency[7]
VDD = 3.3V
–
–
200
MHz
VDD = 2.5V
–
–
170
Tpd
PECL_CLK to Q Delay[7]
VDD = 3.3V
4.0
–
8.6
ns
TCLK to Q Delay[7]
4.2
–
10.5
PECL_CLK to Q Delay[7]
VDD = 2.5V
6.0
–
10.6
TCLK to Q Delay[7]
6.2
–
10.5
FoutDC
Output Duty Cycle[7, 8]
Measured at VDD/2
45
–
55
%
tpZL, tpZH
Output Enable Time (all outputs)
2
–
10
ns
tpLZ, tpHZ
Output Disable Time (all outputs)
2
–
10
ns
Tskew
Output-to-Output Skew[7, 9]
–
250
350
ps
Tskew(pp)
Part-to-Part Skew[10]
PECL_CLK to Q
–
1.5
2.75
ns
TCLK to Q
–
2.0
4.0
Tr/Tf
Output Clocks Rise/Fall Time[9]
0.8V to 2.0V,
VDD = 3.3V
0.10
–
1.0
ns
0.6V to 1.8V,
VDD = 2.5V
0.10
–
1.3
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
VTT
Zo = 50 ohm
VTT
RT = 50 ohm
RT = 50 ohm
CY29949 DUT
Figure 1. LVCMOS_CLK CY29949 Test Reference for VCC = 3.3V and VCC = 2.5V
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
VTT
RT = 50 ohm
CY29949 DUT
Zo = 50 ohm
RT = 50 ohm
VTT
Figure 2. PECL_CLK CY29949 Test Reference for VCC = 3.3V and VCC = 2.5V
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