SWITCHING SPECIFICATIONS AT T

PARAMETER

SYM DEVICE

MIN TYP MAX UNITS

TEST CONDITION

0.2

0.8

µs

R

Το Logic Low at Output ( fig 1 )

Propagation Delay Time

t

PLH

0.2

0.8

µs

R

Το Logic High at Output ( fig 1)

Common Mode Transient

Immunity at Logic High

CM

H

10000

V/

µs

I

Level Output ( fig 2 )

R

Common Mode Transient

Immunity at Logic Low

CM

L

-10000

V/

µs

V

Level Output ( fig 2 )

R

Bandwidth

BW

2

MHz

R

NOTES:-

1.

2.

3.

4.

5.

CURRENT TRANSFER RATIO is defined as the ratio of output collector current,I

input current, I

6.

Device considered a two-terminal device: pins 1,2,3, and 4 shorted together and pins 5,6,7 and 8 shorted

together.

7.

Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on

the leading edge of the common mode pulse V

state (i.e. V

Common mode transient immunity in Logic Low level is the maximum tolerable

(negative) dVcm/dt on the trailing edge of the common mode pulse signal, V

will remain in Logic Low state (i.e. V

8.

The 1.9k

Ω load represents 1 TTL unit load of 1.6mA and the 5.6kΩ pull-up resistor.

9.

The frequency at which the a.c. output voltage is 3dB below the low frequency asymptote.

Propagation Delay Time

t

PHL

FIG.1 SWITCHING TEST CIRCUIT

2

I

0

I

F

V

O

1.5V

100

Ω

1.5V

5V

t

PHL

t

PLH

V

OL

R

L

V

O

C

8

7

6

5

PULSE

GENERATOR

Z

t

I

F

1

4

3

10% Duty Cycle

1/f < 100

µs

5V

DB91008-AAS/A2

7/12/00