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AD9480

Rev. A | Page 16 of 28

APPLICATION NOTES

The AD9480 uses a 1.5-bit per stage architecture. The analog

inputs drive an integrated high bandwidth track-and-hold

circuit that samples the signal prior to quantization by the 8-bit

core. For ease of use, the part includes an on-board reference

and input logic that accepts TTL, CMOS, or LVPECL levels.

The digital output logic levels are LVDS (ANSI 644 compatible).

CLOCKING THE AD9480

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock is combined with the desired signal at the A/D output.

Considerable care has been taken in the design of the CLOCK

input of the AD9480, and the user is advised to give

commensurate thought to the clock source.

The AD9480 has an internal clock duty-cycle stabilization

circuit that locks to the rising edge of CLOCK and optimizes

timing internally for sample rates between 100 MSPS and

250 MSPS. This allows for a wide range of input duty cycles at

the input without degrading performance. Jitter on the rising

edge of the input is still of paramount concern and is not

reduced by the internal stabilization circuit. The duty-cycle

control loop does not function for clock rates less than 70 MHz

nominally. The loop is associated with a time constant that

needs to be considered in applications where the clock rate can

change dynamically, requiring a wait time of 5 µs after a

dynamic clock frequency increase before valid data is available.

The clock duty-cycle stabilizer can be disabled at Pin 28 (S1).

The clock inputs are internally biased to 1.5 V (nominal) and

support either differential or single-ended signals. For best

dynamic performance, a differential signal is recommended. An

MC100LVEL16 performs well in the circuit to drive the clock

inputs (ac coupling is optional). If the clock buffer is greater

than 2 inches from the ADC, a standard LVPECL termination

may be required instead of the simple pull-down termination,

as shown in Figure 30.

AD9480

CLK+

0.1

µF

0.1

µF

510

Ω

510

Ω

PECL

GATE

CLK–

Figure 30. Clocking the AD9480

ANALOG INPUTS

The analog input to the AD9480 is a differential buffer. For best

dynamic performance, impedances at VIN+ and VIN− should

match. Optimal performance is obtained when the analog

inputs are driven differentially. SNR and SINAD performance

can degrade if the analog input is driven with a single-ended

signal; however, performance can be adequate for some

applications (see Figure 6). The analog inputs self-bias to

approximately 1.9 V; this common-mode voltage can be

externally overdriven by approximately ±300 mV if required.

A wideband transformer, such as the Mini-Circuits® ADT1-1WT,

can provide the differential analog inputs for applications that

require a single-ended-to-differential conversion. Note that the

filter and center-tap capacitor on the secondary side is optional

and dependent on application requirements. An RC filter at

the secondary side helps reduce any wideband noise aliased

by the ADC.

AD9480

VIN+

AVDD

(R, C OPTIONAL)

AGND

0.1

µF

10pF

Ω

49.9

Ω

VIN–

Figure 31. Driving the ADC with an RF Transformer

For dc-coupled applications, the AD8138/AD8139 or AD8351

can serve as a convenient ADC driver, depending on

requirements. Figure 32 shows an example with the AD8138.

The AD9480 PCB has an optional AD8351 on board, as shown

in Figure 41 and Figure 42. The AD8351 typically yields better

performance for frequencies greater than 30 MHz to 40 MHz.

AD9480

AD8138

VIN+

AVDD

AGND

0.1

µF

20pF

Ω

VIN–

49.9

Ω

1.3k

Ω

499

Ω

499

Ω

523

Ω

499

Ω

Figure 32. Driving the ADC with the AD8138

Table 8. S1 Voltage Levels

S1 Voltage

Data Format

Duty-Cycle Stabilizer

0.9 × AVDD −> AVDD

Offset binary

Disabled

2/3 AVDD ± (0.1 × AVDD)

Offset binary

Enabled

1/3 AVDD ± (0.1 × AVDD)

Twos complement

Enabled

AGND −> (0.1 × AVDD)

Twos complement

Disabled

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