AD9432

Rev. F | Page 13 of 16

THEORY OF OPERATION

The AD9432 is a 12-bit pipeline converter that uses a switched-

capacitor architecture. Optimized for high speed, this converter

provides flat dynamic performance up to frequencies near

Nyquist. DNL transitional errors are calibrated at final test to

a typical accuracy of 0.25 LSB or less.

ANALOG INPUT

The analog input to the AD9432 is a differential buffer. The

input buffer is self-biased by an on-chip resistor divider that

sets the dc common-mode voltage to a nominal 3 V (see the

Equivalent Circuits section). Rated performance is achieved

by driving the input differentially. The minimum input offset

voltage is obtained when driving from a source with a low

differential source impedance, such as a transformer in ac

applications. Capacitive coupling at the inputs increases the

input offset voltage by as much as ±25 mV. Driving the ADC

single-ended degrades performance. For best dynamic perfor-

mance, impedances at AIN and AIN should match.

Special care was taken in the design of the analog input section

of the AD9432 to prevent damage and corruption of data when

the input is overdriven. The nominal input range is 2 V p-p.

Each analog input is 1 V p-p when driven differentially.

4.0

3.5

2.5

3.0

2.0

AIN

AIN

Figure 26. Full-Scale Analog Input Range

ENCODE INPUT

Any high speed ADC is extremely sensitive to the quality of the

sampling clock provided by the user. A track-and-hold circuit is

essentially a mixer, and any noise, distortion, or timing jitter on

the clock is combined with the desired signal at the ADC output.

For this reason, considerable care has been taken in the design

of the encode input of the AD9432, and the user is advised to

give commensurate thought to the clock source. The encode

input supports differential or single-ended mode and is fully

TTL-/CMOS-compatible.

Note that the encode inputs cannot be driven directly from PECL

easily be accommodated by ac coupling, as shown in Figure 27.

Good performance is obtained using an MC10EL16 translator

in the circuit to drive the encode inputs.

PECL

GATE

ENCODE

AD9432

ENCODE

510Ω

0.1µF

0.1µF

510Ω

Figure 27. AC Coupling to Encode Inputs

ENCODE VOLTAGE LEVEL DEFINITION

The voltage level definitions for driving ENCODE and ENCODE

in single-ended and differential mode are shown in

.

Figure 28

ENCODE

ENCODE

ENCODE

0.1µF

Figure 28. Differential and Single-Ended Input Levels

Table 5. Encode Inputs

Input

Min

Nominal

Max

500 mV

750 mV

3.5 V

0 V

1.25 V

1.6 V

2 V

3.5 V

0 V

0.8 V

Often, the cleanest clock source is a crystal oscillator producing a

pure sine wave. In this configuration, or with any roughly symmet-

rical clock input, the input can be ac-coupled and biased to a

reference voltage that also provides the encode. This ensures

that the reference voltage is centered on the encode signal.