Clock

Uncoded

Bitstream

Machester

Coded

Bitstream

1

0

1

0

1

1

1

0

0

1

1

0

0

0

1

IN

Clipping

Clipping

V

V

2 V

u

ModulatorOutput

AnalogInput

+FS(AnalogInput)

-FS(AnalogInput)

21

AMC1106E05, AMC1106M05

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Feature Description (continued)

8.3.4 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 50 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits of

resolution on the decimation filter, that percentage ideally corresponds to code 58368. A differential input of –50

mV produces a stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with a

16-bit resolution decimation filter. This –50-mV to 50-mV input voltage range is also the specified linear range

FSR of the AMC1106 with performance as specified in this document. If the input voltage value exceeds this

range, the output of the modulator shows nonlinear behavior where the quantization noise increases. The output

of the modulator clips with a stream of only zeros with an input less than or equal to –64 mV or with a stream of

only ones with an input greater than or equal to 64 mV. In this case, however, the AMC1106 generates a single 1

(if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the Fail-

Safe Output section for more details). Figure 45 shows the input voltage versus the modulator output signal.

Figure 45. Analog Input versus AMC1106 Modulator Output

Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception

of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):

(1)

The AMC1106 system clock is provided externally at the CLKIN pin. For more details, see the Switching

Characteristics table and the Manchester Coding Feature section.

8.3.5 Manchester Coding Feature

The AMC1106E05 offers the IEEE 802.3-compliant Manchester coding feature that generates at least one

transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc

components and supports single-wire data and clock transfer without having to consider the setup and hold time

requirements of the receiving device. The Manchester coding combines the clock and data information using

exclusive or (XOR) logical operation. Figure 46 shows the resulting bitstream. The duty cycle of the Manchester

encoded bitstream depends on the duty cycle of the input clock CLKIN.

Figure 46. Manchester Coded Output of the AMC1106E05