AD9203ARURL7 datasheet(5/29 Pages) AD

5 / 29 page

AD9203

Rev. B | Page 4 of 28

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

Two-Tone Intermodulation Distortion

IMD

f = 44.49 MHz and 45.52 MHz

Differential Phase

0.2

Degree

NTSC 40 IRE Ramp

Differential Gain

0.3

DIGITAL INPUTS

High Input Voltage

VIH

2.0

Low Input Voltage

VIL

0.4

Clock Pulse Width High

11.25

Clock Pulse Width Low

11.25

Clock Period2

DIGITAL OUTPUTS

High-Z Leakage

IOZ

± 5.0

µA

Output = 0 to DRVDD

Data Valid Delay

tOD

CL= 20 pF

Data Enable Delay

tDEN

CL= 20 pF

Data High-Z Delay

tDHZ

CL= 20 pF

LOGIC OUTPUT (with DRVDD = 3 V)

High Level Output Voltage (IOH = 50 µA)

VOH

2.95

High Level Output Voltage (IOH = 0.5 mA)

VOH

2.80

Low Level Output Voltage (IOL= 1.6 mA)

VOL

0.3

Low Level Output Voltage (IOL= 50 µA)

VOL

0.05

1 Differential Input (2 V p-p).

2 The AD9203 will convert at clock rates as low as 20 kHz.

N+1

N–1

N+2

N+3

N+4

N+5

N+6

ANALOG

INPUT

DATA

OUT

N–7

N–6

N–5

N–4

TOD = 3ns MIN

7ns MAX

(CLOAD = 20pF)

N–3

N–2

N–1

N+1

CLOCK

Figure 2. Timing Diagram

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