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THS1207CDA Datasheet(PDF) 15 Page - Texas Instruments |
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THS1207CDA Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 30 page ![]() THS1207 SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 www.ti.com 15 To provide the system with channel information, the THS1207 utilizes an active low SYNC signal. When operated in a multichannel configuration, the SYNC signal is active low when data from channel one is available to the databus. When operated in single-channel mode (single-ended or differential operation) the SYNC signal is disabled. Figure 26 shows the timing of the conversion when one analog input channel is selected. The maximum throughput rate is 6 MSPS in this mode. There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be seen in Figure 26 and in the read and SYNC timing table. A more detailed description of the timing is given in the timing section and signal description of the THS1207. Sample N Channel 1 Sample N+2 Channel 1 Sample N+3 Channel 1 Sample N+1 Channel 1 Sample N+4 Channel 1 Sample N+5 Channel 1 Sample N+6 Channel 1 Data N–1 Channel 1 Data N Channel 1 Data N+1 Channel 1 Data N+2 Channel 1 Data N–4 Channel 1 Data N–3 Channel 1 Data N–2 Channel 1 AIN CONV_CLK READ† †READ is the logical combination from CS0, CS1 and RD td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) Figure 26. Conversion Timing in 1-Channel Operation Figure 27 shows the conversion timing when 2 analog input channels are selected. The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is available to the databus. The signal SYNC is active low when data of channel one is available to the databus. The data of channel one is followed by the data of channel two before channel one is again available and the SYNC signal is active low. Sample N Channel 1, 2 Sample N+1 Channel 1, 2 Sample N+2 Channel 1, 2 Sample N+3 Channel 1, 2 Data N–1 Channel 2 Data N Channel 1 Data N Channel 2 Data N+1 Channel 1 Data N–2 Channel 1 Data N–2 Channel 2 Data N–1 Channel 1 AIN CONV_CLK READ† †READ is the logical combination from CS0, CS1 and RD SYNC td(A) td(pipe) tw(CONV_CLKH) tw(CONV_CLKL) tc tsu(CONV_CLKL-READL) tsu(READH-CONV_CLKL) td(CONV_CLKL-SYNCL) td(CONV_CLKL-SYNCH) Figure 27. Conversion Timing in 2-Channel Operation |
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