TMS416809 datasheet(3/28 Pages) TI

3 / 28 page

TMS416809, TMS417809

2097152-WORD BY 8-BIT HIGH-SPEED DRAMS

SMKS885A – DECEMBER 1995 – REVISED MARCH 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

TMS417809

A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing

each of the 2 048 rows (A0 – A10). A normal read or write cycle refreshes all bits in each row that is selected.

A RAS-only operation can be used by holding CAS at the high (inactive) level, conserving power as the output

buffers remain in the high-impedance state. Externally generated addresses must be used for a RAS-only

refresh.

hidden refresh

A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by

holding CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a

RAS-only refresh cycle. The external address is ignored, and the refresh address is generated internally.

CAS-before-RAS ( CBR ) refresh

CBR refresh is performed by bringing CAS low earlier than RAS (see parameter tCSR) and holding it low after

RAS falls (see parameter tCHR). For successive CBR refresh cycles, CAS can remain low while cycling RAS.

The external address is ignored, and the refresh address is generated internally.

power up

To achieve proper device operation, an initial pause of 200

µs followed by a minimum of eight initialization cycles

is required after power up to the full VCC level. These eight initialization cycles must include at least one refresh

( RAS-only or CBR ) cycle.

TMS416809 Datasheet(PDF) 3 Page - Texas Instruments