ADAV801 datasheet(45/61 Pages) AD

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ADAV801

Rev. A | Page 44 of 60

Receiver User Bit Buffer Indirect Address— Address 1010000 (0x50)

Table 81. Receiver User Bit Buffer Indirect Address Register Bit Map

RxUBADDR7

RxUBADDR6

RxUBADDR5

RxUBADDR4

RxUBADDR3

RxUBADDR2

RxUBADDR1

RxUBADDR0

Table 82. Receiver User Bit Buffer Indirect Address Register Bit Descriptions

Bit Name

Description

RxUBADDR[7:0]

Indirect address pointing to the address location in the receiver user bit buffer.

Receiver User Bit Buffer Data—Address 1010001 (0x51)

Table 83. Receiver User Bit Buffer Data Register Bit Map

RxUBDATA7

RxUBDATA6

RxUBDATA5

RxUBDATA4

RxUBDATA3

RxUBDATA2

RxUBDATA1

RxUBDATA0

Table 84. Receiver User Bit Buffer Data Register Bit Descriptions

Bit Name

Description

RxUBDATA[7:0]

A read from this register reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR0[7:0].

This buffer can be written to when autobuffering of the user bits is enabled; otherwise, it is a read-only buffer.

Transmitter User Bit Buffer Indirect Address—Address 1010010 (0x52)

Table 85. Transmitter User Bit Buffer Indirect Address Register Bit Map

TxUBADDR7

TxUBADDR6

TxUBADDR5

TxUBADDR4

TxUBADDR3

TxUBADDR2

TxUBADDR1

TxUBADDR0

Table 86. Transmitter User Bit Buffer Indirect Address Register Bit Descriptions

Bit Name

Description

TxUBADDR[7:0]

Indirect address pointing to the address location in the transmitter user bit buffer.

Transmitter User Bit Buffer Data—Address 1010011 (0x53)

Table 87. Transmitter User Bit Buffer Data Register Bit Map

TxUBDATA7

TxUBDATA6

TxUBDATA5

TxUBDATA4

TxUBDATA3

TxUBDATA2

TxUBDATA1

TxUBDATA0

Table 88. Transmitter User Bit Buffer Data Register Bit Descriptions

Bit Name

Description

TxUBDATA[7:0]

A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0[7:0].

When user bit autobuffering is enabled, this buffer is disabled.

Q Subcode CRCError Status—Address 1010100 (0x54)

Table 89. Q Subcode CRCError Status Register (Read-Only) Bit Map

Reserved

QCRCERROR

QSUB

Table 90. Q Subcode CRCError Status Register (Read-Only) Bit Descriptions

Bit Name

Description

QCRCERROR

This bit is set if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This

bit is cleared once the register is read.

QSUB

This bit is set if a Q subcode has been read into the Q subcode buffer (see Table 91).

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