VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7961

3.125Gb/s PECL Limiting Amplifier with LOS Detect

G52360-0, Rev 2.0

Page 7

02/09/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Detailed Description

The VSC7961 is a high-speed limiting amplifier with Loss of Signal (LOS) detect. The device is designed

to operate with a 3.3V or 5V supply in SDH/SONET and Fibre Channel applications up to 3.125Gb/s. The

VSC7961 has positive emitter-coupled logic (PECL) outputs. The VSC7959 provides the same functionality as

the VSC7961 with current-mode logic (CML) outputs. The key features of the VSC7961 are Loss-of-Signal

(LOS) detect, output offset correction, output squelch, low power supply current, and fast rise and fall times.

The inputs of the device provide 100

Ω input impedance between IN+ and IN- and are intended to be DC-

coupled. The PECL output circuits should be terminated through 50

Ω to V

Loss of Signal (LOS) Detect

This feature utilizes an rms power detector with programmable LOS indicator to provide two outputs, LOS

and LOS. The input TH is used to set the threshold at which the loss of signal detector outputs, LOS and LOS,

change state. See Loss of Signal Specifications (Table 3) for setting the resistor value between TH and ground.

The Loss-of-Signal Truth Table (Table 4) clarifies how LOS and SQUELCH interact.

Optional Squelch

Squelch is disabled when SQUELCH is not connected or is set to TTL low level. When SQUELCH is set to

TTL high level and LOS is asserted, the data outputs, OUT+ and OUT- are forced to static levels. If LOS is not

asserted, the outputs will not be squelched.

Offset Correction

This feature is provided to ensure that the offsets in the amplifier coupled with its gain do not cause the out-

put buffer to give a false output. Because of the high gain of the amplifier, offset correction using a low-fre-

quency feedback loop reduces input offset. If no component is placed between pins CZ1 and CZ2, the low

frequency cut-off is 2MHz. If a 0.1

µF capacitor is placed between CZ1 and CZ2, the low frequency cut-off is

lowered to about 2kHz. For Fibre Channel and Gigabit Ethernet applications, leave pins CZ1 and CZ2 open. For

ATM/SONET and other scrambled non-return-to-zero (NRZ) applications, place a 0.1

µF capacitor between

CZ1 and CZ2. This maintains a one-decade separation between the lowest input frequency and the low fre-

quency cut-off. The low frequency cut-off of the offset correction loop is given by the following equation:

µF + 100pF)

= 1.96kHz