2003 Jun 25

11

Philips Semiconductors

Product specification

Octal D-type transparent latch; 3-state

74ALVC573

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MNA814

th

tsu

th

tsu

VM

VM

VI

GND

VI

GND

LE input

Dn input

Fig.11 Data set-up and hold times for Dn input to LE input.

The shaded areas indicate when the input is permitted to change for predictable output performance.

INPUT

1.65 to 1.95 V

0.5

≤ 2.0 ns

2.3 to 2.7 V

0.5

× V

CC

≤ 2.0 ns

2.7 V

1.5 V

2.7 V

≤ 2.5 ns

3.0 to 3.6 V

1.5 V

2.7 V

≤ 2.5 ns

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VEXT

VCC

VI

VO

MNA616

D.U.T.

CL

RT

RL

RL

PULSE

GENERATOR

Fig.12 Load circuitry for switching times.

Definitions for test circuit:

1.65 to 1.95 V

30 pF

1 k

Ω

open

GND

2

2.3 to 2.7 V

30 pF

500

Ω

open

GND

2

2.7 V

2.7 V

50 pF

500

Ω

open

GND

6 V

3.0 to 3.6 V

2.7 V

50 pF

500

Ω

open

GND

6 V