REV. PrA

PRELIMINARY TECHNICAL DATA

AD9748

–5–

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

27

DB7

Most Significant Data Bit (MSB)

28-32, 1

DB6–DB1

Data Bits 6-1

2

DB0

Least Significant Data Bit (LSB)

25

SLEEP

Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left

unterminated if not used.

23

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO

to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to

AGND). Requires 0.1 µF capacitor to AGND when internal reference activated.

24

FS ADJ

Full-Scale Current Output Adjust

4-9

NC

No Internal Connection

19, 22

ACOM

Analog Common

20

IOUTB

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

21

IOUTA

DAC Current Output. Full-scale current when all data bits are 1s.

17, 18

AVDD

Analog Supply Voltage (3.3 V)

15

MODE2

Selects Input Data Format. Connect to CLKGND for straight binary, CLKVDD for two’s complement.

16

MODE1

Clock Mode Selection. Connect to CLKGND for single ended clock receiver (drive clk+ and float

clk-). Connect to CLKVDD for differential receiver. Float for PECL receiver (terminations

on-chip).

10, 26

DCOM

Digital Common

3

DVDD

Digital Supply Voltage (3.3 V)

12

CLK+

Differential Clock Input.

13

CLK-

Differential Clock Input.

11

CLKVDD

Clock Supply Voltage (3.3 V)

14

CLKCOM

Clock Common

PIN 1

INDICATOR

TOP VIEW

24 FSADJ

23 REFIO

22 ACOM

21 IOUTA

DB1 1

(LSB) DB0 2

DVDD 3

20 IOUTB

19 ACOM

18 AVDD

17 AVDD

NC 4

NC 5

NC 6

NC 7

NC 8

AD9748