AD9736BBC datasheet(22/42 Pages) AD

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AD9736/AD9735/AD9734

Preliminary Technical Data

Rev. PrJ | Page 22 of 42

AD9736 DATA INTERFACE CONTROLLERS

There are 2 internal controllers that can be utilized in the operation

of the AD9736. The first controller helps maintain optimum LVDS

data sampling and the second controller helps maintain optimum

synchronization between the DACCLK and the incoming data. The

LVDS controller is responsible for optimizing the sampling of the

data from the LVDS bus (DB13:0) while the SYNC controller

resolves timing problems between the DAC_CLK (CLK+, CLK-)

and the DATACLK. A block diagram of these controllers is shown

in Figure 23.

The controllers are clocked with a divided down version of the

DAC_CLK. The divide ratio is set utilizing the controller clock

predivider bits (CCD<3:0>) located at REG22 bits 3:0 to generate

the controller clock as follows:

Controller Clock = DAC_CLK / ( 2 ^ ( CCD<3 :0> + 4 ))

NOTE

: The controller clock may not exceed 10MHz for correct

operation. Until CCD<3:0> has been properly programmed to

meet this requirement the DAC output may not be stable.

The LVDS and SYNC controllers can be independently operated in

3 different modes via SPI port REG06 and REG08.

Manual Mode

Surveillance Mode

Auto Mode

In manual mode all of the timing measurements and updates are

externally controlled via the SPI.

In surveillance mode each controller takes measurements and

calculates a new “optimal” value continuously. The result of the

measurement can be passed through an averaging filter before

evaluating the results for increased noise immunity. The filtered

result is compared to a threshold value set via REG06 and REG08

of the SPI port. If the error is greater then the threshold, an

interrupt is triggered and the controller stops. REG01 of the SPI

port controls the interrupts with bits 3 and 2 enabling the

respective interrupts and bits 7 and 6 indicating the respective

controller’s interrupt. If an interrupt is enabled it will also activate

the AD9736’s IRQ pin. In order to clear an interrupt the interrupt

enable bit of the respective controller must be set to a zero for at

least one controller clock cycle (controller clock < 10MHz).

Auto mode is almost identical to surveillance mode. Instead of

triggering an interrupt and stopping the controller, the controller

automatically updates its settings to the newly calculated “optimal”

value and continues to run.

Figure 23.AD9736 Internal Synchronization Engine

Data Source

i.e. FPGA

LVDS

SAMPLE

LOGIC

FIFO

SYNC

LOGIC

DAC

DACCLK

DATACLK_OUT

DB<13:0>

DATACLK_IN

CLK Control

LVDS

Controller

SYNC

Controller

Data Source

i.e. FPGA

LVDS

SAMPLE

LOGIC

FIFO

SYNC

LOGIC

DAC

DACCLK

DATACLK_OUT

DB<13:0>

DATACLK_IN

CLK Control

LVDS

Controller

SYNC

Controller

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