ADP3417 datasheet(2/8 Pages) AD

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REV. A

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ADP3417–SPECIFICATIONS1

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

SUPPLY

Supply Voltage Range

VCC

4.15

13.2

Quiescent Current

ISYS

VCC = BST = 12 V, IN = 0 V

PWM INPUT

Input Voltage High

2.5

Input Voltage Low

0.8

HIGH SIDE DRIVER

Output Resistance, Sourcing Current

VBST – VSW = 12 V

1.75

3.0

Ω

Output Resistance, Sinking Current

VBST – VSW = 12 V

1.0

2.5

Ω

Transition Times

trDRVH

See Figure 2, VBST – VSW = 12 V,

CLOAD = 3 nF

Transition Times

tfDRVH

See Figure 2, VBST – VSW = 12 V,

CLOAD = 3 nF

Propagation Delay

3, 4

tpdhDRVH

See Figure 2, VBST – VSW = 12 V,

tpdlDRVH

VBST – VSW = 12 V

LOW SIDE DRIVER

Output Resistance, Sourcing Current

VCC = 12 V

1.75

3.0

Ω

Output Resistance, Sinking Current

VCC = 12 V

1.0

2.5

Ω

Transition Times

trDRVL

See Figure 2, VCC = 12 V,

CLOAD = 3 nF

tfDRVL

See Figure 2, VCC = 12 V,

CLOAD = 3 nF

Propagation Delay

3, 4 (See Figure 2)

tpdhDRVL

See Figure 2, VCC = 12 V

tpdlDRVL

See Figure 2, VCC = 12 V

NOTES

1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.

2Logic inputs meet typical CMOS I/O conditions for source/sink current (~1

µA).

3AC specifications are guaranteed by characterization but not production tested.

4For propagation delays, “TPDH” refers to the specified signal going high; “TPDL” refers to it going low.

Specifications subject to change without notice.

(VCC = 12 V, BST = 4 V to 26 V, TA = 0 C to 70 C, unless otherwise noted.)

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