AN727

Vishay Siliconix

www.vishay.com

S FaxBack 408-970-5600

2

Document Number: 70959

07-Jul-99

FUNCTIONAL BLOCK DIAGRAM

FIGURE 2.

Reference

Threshold

Generator

Soft-Start

Timer

Oscillator

–

+

UVLO

POR

Bias

Generator

OTP

System Monitor

Drivers

PWM/PFM

Select

PWM

Modulator

PSM

Modulator

0.5 V

1.0 V

Ramp

FB

COMP

SYNC

CLK

POKIN

POK

PWM/PSM

GND

PGND

SD

COIL

Negative Return

and

Substrate

Positive Supply

1.3 V

DESIGN GUIDELINES

The following section describes key device features and

provides general guidelines for designing a buck regulator with

the Si9167.

Voltage Mode Control

For cellular phone and PDA applications, voltage-mode

control provides a number of advantages, including the

avoidance of power dissipation in current sensing elements,

greater noise immunity (since the PWM signal can be as high

as 1 V), and a less complicated single feedback loop to

compensate with.

The BiCMOS process used in the Si9167 improves

voltage-mode performance by increasing the operating

frequency and thereby pushing the closed loop bandwidth to

more than 100 kHz. Since the intended applications for this

device involves a battery input, such that rapid changes in

voltage level are not involved, there is no need for a fast input

dynamic response as offered by current mode control.

FIGURE 3. Voltage Mode Control

0.5 V

1.0 V

+

–

Oscillator