LM5025ASD datasheet(3/16 Pages) NSC

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Pin Description (Continued)

NAME

DESCRIPTION

APPLICATION INFORMATION

OUT_A

Main output driver

Output of the main switch PWM output gate driver.

Output capability of 3A peak sink current.

OUT_B

Active Clamp output driver

Output of the Active Clamp switch gate driver.

Capable of 1.25A peak sink current..

PGND

Power ground

Connect directly to analog ground.

AGND

Analog ground

Connect directly to power ground. For the LLP

package option the exposed pad is electrically

connected to AGND.

Soft-start control

An external capacitor and an internal 20µA current

source set the softstart ramp. The SS current source

is reduced to 1uA initially following a CS2

over-current event or an over temperature event.

COMP

Input to the Pulse Width Modulator

An internal 5K

Ω resistor pull-up is provided on this

pin. The external opto-coupler sinks current from

COMP to control the PWM duty cycle.

Oscillator timing resistor pin

An external resistor connected from RT to ground

sets the internal oscillator frequency.

SYNC

Oscillator UP/DOWN synchronization input

The internal oscillator can be synchronized to an

external clock with a frequency 20% lower than the

internal oscillator’s free running frequency. There is

no constraint on the maximum sync frequency.

UVLO

Line Under-Voltage shutdown

An external voltage divider from the power source

sets the shutdown comparator levels. The

comparator threshold is 2.5V. Hysteresis is set by an

internal current source (20µA) that is switched on or

off as the UVLO pin potential crosses the 2.5V

threshold.

Exposed PAD, underside of the LLP package

option

Internally bonded to the die substrate. Connect to

GND potential for low thermal impedance.

LM5025ASD Datasheet(PDF) 3 Page - National Semiconductor (TI)

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