AD2S1205 datasheet(14/21 Pages) AD

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AD2S1205

Rev. A | Page 13 of 20

RD Input

CS Input

The 12-bit data bus lines are normally in a high impedance

state. The output buffer is enabled when CS and RD are held

low. A falling edge of the RD signal transfers data to the output

buffer. The selected data is made available to the bus to be read

within t6 of the RD pin going low. The data pins return to a high

impedance state when the RD pin returns to a high state within

t7. When reading data continuously, wait a minimum of t3 after

RD is released before reapplying it.

The device is enabled when CS is held low.

RDVEL Input

RDVEL input is used to select between the angular position

Figure 7

RDVEL is held high to select the angular position register and

low to select the angular velocity register. The RDVEL pin must

be set (stable) at least t4 before the RD pin is pulled low.

fCLKIN

CLKIN

DATA

DON'T CARE

VELOCITY

POSITION

SAMPLE

RDVEL

Figure 7. Parallel Port Read Timing

Table 6. Parallel Port Timing

Parameter

Description

Min

Typ

Max

Unit

fCLKIN

Frequency of clock input

6.144

8.192

10.24

MHz

SAMPLE pulse width

2 × (1/fCLKIN) + 20

Delay from SAMPLE before RD/CS low

6 × (1/fCLKIN) + 20

RD pulse width

Set time RDVEL before RD/CS low

Hold time RDVEL after RD/CS low

Enable delay RD/CS low to data valid

Disable delay RD/CS low to data high-Z

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