CLOCK

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RAL T RON EL ECT R ONICS CORP.

! 10651 N . W . 19

phone: (305) 593-6033

! fax: (305) 594-3973 ! e-mail: sales@raltron.com ! WEB: http://www.raltron.com

CLD/CLDP SERIES: CLOCK OSCILLATOR, LVDS, +3.3 VDC or +2.5VDC

DESCRIPTION: A crystal controlled, high frequency, highly stable oscillator, adhering to Low Voltage

Differential Signaling (LVDS) Standards. The output can be Tri-stated to facilitate testing or combined multiple

clocks. The device is contained in a sub-miniature, very low profile, leadless ceramic SMD package with 6 gold

contact pads. This miniature oscillator is ideal for today's automated assembly environments.

APPLICATIONS AND FEATURES:

" Infiniband; 10GbE; Network Processors; SOHO Routing; Switches; WAN Interfaces

" Common Frequencies: 106.25 MHz; 125 MHz; 150 MHz; 155.52 MHz; 156.25 MHz; 161.1328 MHz

" +3.3 VDC or +2.5VDC LVDS

" Frequency Range from 50.000 to 315 MHz

" No multiplication

" Miniature Ceramic SMD Package Available on Tape and Reel

" Lead Free and ROHS Compliant

$

$

$

$ ABSOLUTE MAXIMUM RATINGS:

PARAMETER

SYMBOL

VALUE

UNIT

Operating temperature range

Ta

-40…+85

°C

Storage temperature range

T(stg)

-55…+90

°C

Supply voltage

Vcc

-0.5…+5.0

VDC

Maximum Input Voltage

Vi

Vss-0.5…Vcc+0.5

VDC

Maximum Output Voltage

Vo

Vss-0.5…Vcc+0.5

VDC

$

$

$

$ ELECTRICAL PARAMETERS:

PARAMETER

SYMBO

L

TEST CONDITIONS

*1

VALUE

UNIT

Nominal Frequency

fo

50.000 ~ 315.00**

MHz

Supply Voltage

Vcc

+3.3 or +2.5

±5%

VDC

Supply Current

Is

80.0 MAX

mA

Output Logic Type

LVDS

Load

Connected between Out and Complementary Out

100

Ω

Voh

Output logic high

1.43 Typ, 1.6 Max

VDC

Vol

Output logic low

0.9 Min, 1.10 Typ

VDC

Vod

Differential output

247 Min, 330 Typ, 454 Max

mV

Differential output error

50 Max

mV

VOS

Offset Voltage

1.125 Min, 1.25 Typ, 1.375 Max

VDC

Output Levels

OS

Offset error

50 Max

mV

Duty Cycle

DC

Measured at 50% of Vcc

40/60 to 60/40 or 45/55 to 55/45

%

Rise / Fall Time

tr / tf

Measured at 20/80% and 80/20% Vcc Levels

0.6 TYP

*2

ns

Integrated Phase tji RMS, Fj = 12 kHz…20 MHz

0.3 TYP**

ps

Integrated Phase RMS tii offset frequency 50KHz to

80MHz

0.5 TYP**

ps

Deterministic period Jitter tdj using wavecrest analyz.

0.0TYP **

ps

Random period Jitter trj using wavecrest analyz.

2.5 TYP **

ps

Jitter

J

Peak to Peak Jitter Tp-p using wavecrest analyz.

25 TYP**

ps

Phase Noise typ.

@155.52MHz

£(

∆f)

£(

∆f)

£(

∆f)

£(

∆f)

∆f=10 Hz

∆f=1 KHz

∆f=10 KHz

∆f ≥100 KHz

-65

-120

-140

-145

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

Overall Frequency Stability

∆f/fc

Op. Temp., Aging, Load, Supply and Cal. Variations

Ppm

Pin 1

Output Enabled

Output Disabled

En

Dis

High Voltage or No Connect

Ground

0.7

•Vcc MIN

0.3

•Vcc MAX

VDC

VDC

*1 Test Conditions Unless Stated Otherwise: Nominal Vcc, Nominal Load, +25

±3°C

*2 Frequency Dependent

*3 Not All Stabilities Available With All Temperature Ranges—Please Consult Factory For Availability