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Z8937116FSC Datasheet(PDF) 18 Page - Zilog, Inc. |
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Z8937116FSC Datasheet(HTML) 18 Page - Zilog, Inc. |
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18 / 40 page ![]() Z89321/371/391 16-Bit Digital Signal Processors Zilog 18 P R E L I M I N A R Y DS97DSP0100 ADDRESS SPACE Program Memory. Programs of up to 4 K words can be masked into internal ROM (OTP for Z89371). Four loca- tions are dedicated to the vector address for the three in- terrupts (0FFDH-0FFFH) and the starting address follow- ing a Reset (0FFCH). Internal ROM is mapped from 0000H to 0FFFH, and the highest location for program is 0FFBH. A 64 K word External Program Memory Space is available on the Z89391. The vector addresses for the Z89391 re- side at FFFCH-FFFFH (Figure 15). Internal Data RAM. The Z89321, 371 and 391 all have in- ternal 512 x 16-bit word data RAM organized as two banks of 256 x 16-bit words each: RAM0 and RAM1. Each data RAM bank is addressed by three pointers: Pn:0 (n = 0-2) for RAM0 and Pn:1 (n = 0-2) for RAM1. The RAM address- es for RAM0 and RAM1 are arranged from 0-255 and 256- 511, respectively. The address pointers, which may be written to, or read from, are 8-bit registers connected to the lower byte of the internal 16-bit D-Bus and are used to per- form modulo addressing. Three addressing modes are available to access the Data RAM: register indirect, direct addressing, and short form direct. The contents of the RAM can be read to, or written from, in one machine cycle per word, without disturbing any internal registers or status other than the RAM ad- dress pointer used for each RAM. The contents of each RAM can be loaded simultaneously into the X and Y inputs of the multiplier. Registers. The Z89321 has 19 internal registers and up to an additional eight external registers. The external regis- ters are user-definable for peripherals, such as A/D or D/A, or to DMA, or other addressing peripherals. Both external and internal registers are accessed in one machine cycle. Figure 14. External Program Memory Port Timing TCY PDSET PDHOLD Valid Valid Valid Valid Valid Valid PASET CLOCK PROGRAM ADDRESS PROGRAM DATA Figure 15. Memory Map Data Memory Not Used DRAM1 DRAM0 01FF 0100 00FF 0000 FFFF Program Memory Not Used INT0-INT2 Vect. RESET Vector 0FFF 0FFC 0000 FFFF FFFC 4 Kwords Or INT0-INT2 Vect. RESET Vector 64 Kwords 512 words On-Chip Memory Off-Chip Memory |
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