74AC843 datasheet(2/10 Pages) NSC

2 / 10 page

Functional Description

The ’AC’ACT843 consists of nine D-type latches with

TRI-STATE outputs The flip-flops appear transparent to the

data when Latch Enable (LE) is HIGH This allows asyn-

chronous operation as the output transition follows the data

in transition On the LE HIGH-to-LOW transition the data

that meets the setup times is latched Data appears on the

bus when the Output Enable (OE) is LOW When OE is

HIGH the bus output is in the high impedance state In

addition to the LE and OE pins the ’AC’ACT843 has a

Clear (CLR) pin and a Preset (PRE) pin These pins are ideal

for parity bus interfacing in high performance systems

When CLR is LOW the outputs are LOW if OE is LOW

When CLR is HIGH data can be entered into the latch

When PRE is LOW the outputs are HIGH if OE is LOW

Preset overrides CLR

Function Tables

Inputs

Internal

Outputs

Function

CLR

PRE

High Z

Latched

Transparent

Latched

Preset

Clear

Preset

ClearHigh Z

PresetHigh Z

H e HIGH Voltage Level

L e LOW Voltage Level

X e Immaterial

Z e High Impedance

NC e No Change

Logic Diagram

TLF9800 – 5

74AC843 Datasheet(PDF) 2 Page - National Semiconductor (TI)