2

Precision Edge™

SY89871U

Micrel

M9999-062904

hbwhelp@micrel.com or (408) 955-1690

PACKAGE/ORDERING INFORMATION

Ordering Information

Package

Operating

Package

Part Number

Type

Range

Marking

SY89871UMI

MLF-16

Industrial

871U

MLF-16

Industrial

871U

Note:

1. Tape and Reel.

Pin Number

Pin Name

Pin Function

1, 2, 3, 4

QB0, /QB0

Differential Buffered Output Clocks: This differential output is a divided-down version of

QB1, /QB1

the input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16.

See “Truth Table.” Unused output pairs may be left floating.

5, 6

QA, /QA

Differential Buffered Undivided Output Clock.

7, 14

VCC

Positive Power Supply: Bypass with 0.1

µF0.01µF low ESR capacitors.

8

/RESET

Output Reset: Internal 25k

Ω pull-up. Logic LOW will reset the divider select. See “Truth

Table.” Input threshold is V

12, 9

IN, /IN

Differential Input: Internal 50

Ω termination resistors to VT input. See “Input Interface

Applications” section.

10

VREF-AC

Reference Voltage: Equal to V

Maximum sink/source current is 0.5mA. See “Input Interface Applications” section.

11

VT

Termination Center-Tap: For CML and LVDS inputs, leave this pin floating. Otherwise,

see “Input Interface Application” section.

13

GND

Ground.

15, 16

S1, S0

Select Pins: See “Truth Table.” LVTTL/CMOS logic levels. Internal 25k

Ω pull-up resistor.

Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is V

PIN DESCRIPTION

1

2

3

4

12

11

10

9

16 15 14 13

5678

QB0

/QB0

QB1

/QB1

IN

VT

VREF-AC

/IN

16-Pin MLF™ (MLF-16)

/RESET

S1

S0

Bank A Output

Bank B Outputs

1

0

0

Input Clock

Input Clock

÷2

1

0

1

Input Clock

Input Clock

÷4

1

1

0

Input Clock

Input Clock

÷8

1

1

1

Input Clock

Input Clock

÷16

0

X

X

Input Clock

QB = LOW, /QB = HIGH

TRUTH TABLE