AR0230CS datasheet(21/24 Pages) ONSEMI

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AR0230CS

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POWER−ON RESET AND STANDBY TIMING

Power−Up Sequence

The

recommended

power−up

sequence

for

the

AR0230CS is shown in Figure 11. The available power

supplies (VDD_IO, VDD, VDD_SLVS, VDD_PLL, VAA,

VAA_PIX) must have the separation specified below.

1. Turn on VDD_PLL power supply.

2. After 100

μs, turn on VAA and VAA_PIX power

supply.

3. After 100

μs, turn on VDD_IO power supply.

4. After 100

μs, turn on VDD power supply.

5. After 100

μs, turn on VDD_SLVS power supply.

6. After the last power supply is stable, enable

EXTCLK.

7. Assert RESET_BAR for at least 1ms. The parallel

interface will be tri−stated during this time.

8. Wait 150000 EXTCLKs (for internal initialization

into software standby.

9. Configure PLL, output, and image settings to

desired values.

10. Wait 1ms for the PLL to lock.

11. Set streaming mode (R0x301a[2] = 1).

Figure 11. Power Up

Hard Reset

Internal

Initialization

Software

Standby

PLL Lock

Streaming

VDD_PLL (2.8)

VAA_PIX

VAA_(2.8)

VDD_IO (1.8/2.8)

VDD(1.8)

VDD_SLVS (0.4)

EXTCLK

RESET_BAR

Table 20.

POWER−UP SEQUENCE

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX

100

−

VAA/VAA_PIX to VDD_IO

100

−

VDD_IO to VDD

100

−

VDD to VDD_SLVS

100

−

Xtal settle time

−

Hard Reset

–

−

Internal Initialization

150000

–

−

EXTCLKs

PLL Lock Time

–

−

12. Xtal settling time is component−dependent, usually taking about 10 – 100 ms.

13. Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the

RC time must include the all power rail settle time and Xtal settle time.

14. It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the

others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high

current draw on this supply.

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