VSP2267 datasheet(13/88 Pages) TI

13 / 88 page

Theory of Operation

SBES001—December 2002

VSP2267

An on-chip V-rate timing generator creates all the signals that are required for specific CCD image sensors.

The TG contains the line and pixel counters used to generate V-rate timing. Figure 2–2 is the block diagram

of the line and pixel counter circuit. A maximum of 2047 lines and 4095 pixels per line are supported in time

scale.

Decoder

H[10:0]

P[12:0]

RST

Line Counter

(MAX 2047 lines)

clk

13 Bit

RST

Pixel Counter

(MAX 4095 Pixels)

clk

11 Bit

F/F

SYSRST

MCLK

Figure 2–2. VSP2267 Line and Pixel Counter Circuit Block Diagram

Figure 2–3 shows a V-rate timing generator block diagram. By one H (horizontal line) before CCD readout,

serial data transfer must be completed by the user, and data must be loaded in the registers containing CCD

model, operation mode, integration time, and electronic zoom area information. Just before CCD readout,

information in the registers is supplied automatically to the decoder, which generates the V-rate signal using

line counter and pixel counter data. Not only the signals used for the CCD, but also the strobe light control

signal is supported. CPOB, CLPD, and PBLK can select either the internal generation mode or the external

supply mode.

VSP2267 Datasheet(PDF) 13 Page - Texas Instruments