AD8021 datasheet(16/20 Pages) AD

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AD8021

With the AD8021, a variety of trade-offs can be made to fine-tune

its dynamic performance. Sometimes more bandwidth or slew

rate is needed at a particular gain. Reducing the compensation

capacitance, as illustrated in TPC 3, will increase the bandwidth

and peaking due to a decrease in phase margin. On the other hand,

if more stability is needed, increasing the compensation cap will

decrease the bandwidth while increasing the phase margin.

As with all high speed amplifiers, parasitic capacitance and induc-

tance around the amplifier can affect its dynamic response.

Often, the input capacitance (due to the op amp itself, as well

as the PC board) could have a significant effect. The feedback

resistance, together with the input capacitance, may contribute to

a loss of phase margin, thereby affecting the high frequency response,

as shown in TPC 10. Furthermore, a capacitor (CF) in parallel

with the feedback resistor can compensate for this phase loss.

Additionally, any resistance in series with the source will create

a pole with the input capacitance (as well as dampen high fre-

quency resonance due to package and board inductance and

capacitance), the effect of which is shown in TPC 11.

It must also be noted that increasing resistor values will increase

the overall noise of the amplifier, and that reducing the feedback

resistor value will increase the load on the output stage, thus

increasing distortion (TPC 18).

Using the Disable Feature

When Pin 8 (

DISABLE) is approximately 2 V or more higher than

Pin 1 (LOGIC REFERENCE), the part is enabled. When Pin 8

is brought down to within about 1.5 V of Pin 1, the part is dis-

abled. See the Specification tables for exact disable and enable

voltage levels. If the disable feature is not going to be used, Pin 8

can be tied to VS or a logic high source, and Pin 1 can be tied to

ground or logic low. Alternatively, if Pin 1 and Pin 8 are not

connected, the part will be in an enabled state.

THEORY OF OPERATION

The AD8021 is fabricated on the second generation of Analog

Devices’ proprietary High Voltage eXtra-Fast Complementary

Bipolar (XFCB) process, which enables the construction of PNP

and NPN transistors with similar fTs in the 3 GHz region. The

transistors are dielectrically isolated from the substrate (and each

other), eliminating the parasitic and latch-up problems caused

by junction isolation. It also reduces nonlinear capacitance

(a source of distortion) and allows a higher transistor fT for a

given quiescent current. The supply current is trimmed, which

results in less part-to-part variation of bandwidth, slew rate,

distortion, and settling time.

As shown in Figure 6, the AD8021 input stage consists of an NPN

differential pair in which each transistor operates at 0.8 mA collec-

tor current. This allows the input devices a high transconductance;

thus, the AD8021 has a low input noise of 2.1 nV/

√Hz @ 50 kHz.

The input stage drives a folded cascode that consists of a pair of

PNP transistors. The folded cascode and current mirror provide

a differential to single-ended conversion of signal current. This

current then drives the high impedance node (Pin 5), where the

CC external capacitor is connected. The output stage preserves

this high impedance with a current gain of 5,000, so that the

AD8021 can maintain a high open-loop gain even when driving

heavy loads.

Two internal diode clamps across the inputs (Pins 2 and 3) protect

the input transistors from large voltages that could otherwise cause

emitter-base breakdown, which would result in degradation of

offset voltage and input bias current.

OUTPUT

+VS

–VS

+IN

–IN

CINTERNAL

1.5pF

CCOMP

Figure 6. Simplified Schematic

PCB LAYOUT CONSIDERATIONS

As with all high speed op amps, achieving optimum performance

from the AD8021 requires careful attention to PC board layout.

Particular care must be exercised to minimize lead lengths

between the ground leads of the bypass capacitors and between

the compensation capacitor and the negative supply. Otherwise,

lead inductance can influence the frequency response and even

cause high frequency oscillations. Use of a multilayer printed

circuit board, with an internal ground plane, will reduce ground

noise and enable a compact component arrangement.

Due to the relatively high impedance of Pin 5 and low values of

the compensation capacitor, a guard ring is recommended. The

guard ring is simply a PC trace that encircles Pin 5 and is

connected to the output, Pin 6, which is at the same potential as

Pin 5. This serves two functions. It shields Pin 5 from any local

circuit noise generated by surrounding circuitry. It also mini-

mizes stray capacitance, which would tend to otherwise reduce

the bandwidth. An example of a guard ring layout may be seen

in Figure 7.

Also shown in Figure 7, the compensation capacitor is located

immediately adjacent to the edge of the AD8021 package, spanning

Pin 4 and Pin 5. This capacitor must be a high quality surface-

mount COG or NPO ceramic. The use of leaded capacitors is not

recommended. The high frequency bypass capacitor(s) should

be located immediately adjacent to the supplies, Pins 4 and 7.

To achieve the shortest possible lead length at the inverting

input, the feedback resistor RF is located beneath the board and

just spans the distance from the output, Pin 6, to inverting input

Pin 2. The return node of resistor RG should be situated as

closely as possible to the return node of the negative supply

bypass capacitor connected to Pin 4.

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