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AT43USB380 Upgrade Map Summary

3420AS–USB–03/04

USB functionality. Communication with the AT43USB380 is achieved through a small

set (less than 25) of high level, ANSI C-compliant APIs. The actual USB protocol includ-

ing HNP and SRP is transparent to the host processor.

AT43USB380 OTG Processor Pin Description

Table 1 gives the description of the pins.

Table 1. Pin Description of the AT43USB380

Signal Name

Dir.

Polarity

Width

Description

System Interface

SYS_CLK

I

1

Host system clock input for synchronization

of WAIT_N and DREQ_N. (Synchronization

requirement can be enable/disable through

internal register settings)

A[7:0]

I

8

System Address Bus

CS_N

I

LO

1

CHIP_SELECT signal from System (ARM

D[15:0]

B

16

System Data Bus [15:0]

D[31:16]/

GPIO[15:0]

B16

BWIDTH[1:0]=1x : System Data Bus [31:16]

BWIDTH[1:0]=0x : GPIO[15:0]

DACK_N

I

LO

1

DMA Acknowledge from System (ARM)

DREQ_N

O

LO

1

DMA Request to System (ARM)

INTR_OUT

O

HI

1

Interrupt to System (ARM)

OE_N

I

LO

1

OUTPUT_ENABLE from System (ARM)

WAIT_N

O

LO

1

WAIT to System (ARM)

WE_N

I

LO

1

WRITE_ENABLE from System (ARM)

BWIDTH[1:0]

I

2

System Data Bus Size:

00 : 8 Bit Interface D[7:0]

01 : 16 Bit Interface D[15:0]

1x : 32 Bit Interface D[31:0]

WAKEUP_N

I

LO

1

Wakeup Request from System

USB Interface

DM

B

1

USB Line (D-)

DP

B

1

USB Line (D+)

ID

I

1

OTG device type identification; used to

differentiate a Mini-A and Mini-B plug

RPU_EN

O

1

Enable resistive pull-up to the D+ line

RPD_EN

O

1

Enable resistive pull-down to the D+/D- lines

Charge Pump Interface

CPClk

O

1

Charge Pump clock output

EN

O

1

Charge Pump; Enable for Charge Pump

PUMP_EN

O

1

Charge Pump; Enable for Charge Pump