AD7643 datasheet(18/29 Pages) AD

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AD7643

Rev. 0 | Page 17 of 28

TYPICAL CONNECTION DIAGRAM

Figure 23 shows a typical connection diagram for the AD7643.

Different circuitry shown in this diagram is optional and is

discussed in the following sections.

ANALOG INPUTS

Figure 24 shows an equivalent circuit of the input structure of

the AD7643.

The two diodes, D1 and D2, provide ESD protection for the

analog inputs IN+ and IN−. Care must be taken to ensure that

the analog input signal never exceeds the supply rails by more

than 0.3 V, because this causes the diodes to become forward-

biased and to start conducting current. These diodes can handle

a forward-biased current of 100 mA maximum. For instance,

these conditions could eventually occur when the input buffer’s

U1 or U2 supplies are different from AVDD. In such a case, an

input buffer with a short-circuit current limitation can be used

to protect the part.

RIN

CIN

IN+ OR IN–

AGND

AVDD

CPIN

Figure 24. AD7643 Simplified Analog Input

The analog input of the AD7643 is a true differential structure.

By using this differential input, small signals common to both

inputs are rejected, as shown in Figure 25, representing the

typical CMRR over frequency with internal and external references.

10000

FREQUENCY (kHz)

100

1000

INT REF

EXT REF

Figure 25. Analog Input CMRR vs. Frequency

During the acquisition phase for ac signals, the impedance of

the analog inputs, IN+ and IN−, can be modeled as a parallel

combination of capacitor CPIN and the network formed by the

series connection of RIN and CIN. CPIN is primarily the pin

capacitance. RIN is typically 175 Ω and is a lumped component

comprised of some serial resistors and the on resistance of the

switches. CIN is typically 12 pF and is mainly the ADC sampling

capacitor. During the conversion phase, when the switches are

opened, the input impedance is limited to CPIN. RIN and CIN

make a 1-pole, low-pass filter that has a typical −3 dB cutoff

frequency of 50 MHz, thereby reducing an undesirable aliasing

effect and limiting the noise coming from the inputs.

Because the input impedance of the AD7643 is very high, the

AD7643 can be driven directly by a low impedance source

without gain error. To further improve the noise filtering achieved

by the AD7643’s analog input circuit, an external 1-pole RC

filter between the amplifier’s outputs and the ADC analog

inputs can be used, as shown in Figure 23. However, large source

impedances significantly affect the ac performance, especially

the total harmonic distortion (THD). The maximum source

impedance depends on the amount of THD that can be

tolerated. The THD degrades as a function of the source

impedance and the maximum input frequency, as shown in

Figure 26.

–70

–110

100

1000

INPUT FREQUENCY (kHz)

RS = 500Ω

RS = 100Ω

RS = 10Ω

RS = 50Ω

–75

–80

–85

–90

–95

–100

–105

Figure 26. THD vs. Analog Input Frequency and Source Resistance

MULTIPLEXED INPUTS

When using the full 1.25 MSPS throughput in multiplexed

applications for a full-scale step, the RC filter, as shown in

Figure 23, does not settle in the required acquisition time, t8.

These values are chosen to optimize the best SNR performance

of the AD7643. To use the full 1.25 MSPS throughput in

multiplexed applications, the RC should be adjusted to satisfy t8

(which is ~ 8.5 × RC time constant). However, lowering R and C

increases the RC filter bandwidth and allows more noise into the

AD7643, which degrades SNR. To preserve the SNR performance

in these applications using the RC filter shown in Figure 23,

the AD7643 should be run with t8 > 350 ns; or approximately

1/(t7 + t8) ~ 1.12 MSPS.

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