CY2V995
Document #: 38-07435 Rev. *A
Page 6 of 10
tSKEW0
Output-Output Skew[10]
Skew between the earliest and the latest
output transitions among all outputs.
–
200
ps
tSKEW1
Skew between the earliest and the latest
output transitions among all same class
outputs.
–
200
ps
tSKEW2
Skew between the nominal output rising
edge to the inverted output falling edge
–
500
ps
tSKEW3
Skew between non-inverted outputs
running at different frequencies
–
500
ps
tSKEW4
Skew between nominal to inverted outputs
running at different frequencies
–
500
ps
tSKEW5
Skew between nominal outputs at different
power supply levels
–
650
ps
tPART
Part-Part Skew
Skew between the outputs of any two
devices under identical settings and
conditions (VDDQ,VDD,temp,air flow,
frequency, etc)
–
750
ps
tPD0
Ref to FB Propagation Delay[11]
–250
+250
ps
tODCV
Output Duty Cycle
Measured at VDD/2
45
55
%
tPWH
Output High Time Deviation
from 50%
Measured at 2.0V for VDD = 3.3V and at
1.7V for VDD = 2.5V.
–1.5
ns
tPWL
Output Low Time Deviation
from 50%
Measured at 0.8V for VDD = 3.3V and at
0.7V for VDD = 2.5V.
–2.0
ns
tR/tF
Output Rise/Fall Time
Measured at 0.8V-2.0V for VDD = 3.3V
and 0.7V–1.7V for VDD = 2.5V
0.15
1.5
ns
tLOCK
PLL lock time[12, 13]
–0.5
ms
tCCJ
Cycle-Cycle Jitter
Divide by 1 output frequency, FS = L, FB
= divide by any
–
100
ps
Divide by 1 output frequency, FS = M/H,
FB = divide by any
–
150
ps
Notes:
11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V–2.0V.
12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits.
13. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.
Switching Characteristics (continued)
Parameter
Description
Condition
Min.
Max.
Unit
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