DS3144N datasheet(63/88 Pages) DALLAS

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DS3141/DS3142/DS3143/DS3144 Single/Dual/Triple/Quad DS3/E3 Framers

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7.11.1 FEAC Register Description

Table 7-I. FEAC Register Map

ADDR

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

60h

FCR

N/A

RFR

TFS1

TFS0

61h

FSR

N/A

RFFE

RFI

RFCD

TFI

62h

FSRL

N/A

RFFOL

RFFNL

RFIL

RFCDL

TFIL

63h

FSRIE

N/A

RFFOIE

RFFNIE

RFIIE

RFCDIE

TFIIE

64h

TFEACA

N/A

TFCA5

TFCA4

TFCA3

TFCA2

TFCA1

TFCA0

65h

TFEACB

N/A

TFCB5

TFCB4

TFCB3

TFCB2

TFCB1

TFCB0

66h

RFEAC

N/A

RFF5

RFF4

RFF3

RFF2

RFF1

RFF0

FCR

FEAC Control Register

60h

Bit #

Name

N/A

RFR

TFS1

TFS0

Default

—

Bits 0, 1: Transmit FEAC Codeword Select Bits 0 and 1 (TFS[1:0]). These two bits control which of the two

available codewords are to be generated. Both TFS0 and TFS1 are edge-triggered; a change from 00 to any other

value starts the desired FEAC transmission. Actions 01 and 10 continue to completion even if TFS is subsequently

written with 00. Action 11 transmits at least 10 codewords before being terminated by TFS = 00. To initiate a new

action, the host must select the idle state (TFS = 00) before selecting the new action.

TFS[1:0]

ACTION

Idle state; do not generate a FEAC codeword (send all ones)

Send codeword A 10 times followed by all ones

Send codeword A 10 times followed codeword B 10 times followed by all ones

Send codeword A continuously (sent at least 10 times)

Bit 2: Receive FEAC Reset (RFR). A 0-to-1 transition resets the FEAC receiver and flushes the receive FEAC

FIFO. This bit must be cleared before generating a subsequent reset.

FSR

FEAC Status Register

61h

Bit #

Name

N/A

RFFE

RFI

RFCD

TFI

Default

—

Bit 0: Transmit FEAC Idle (TFI). This real-time status bit is set when the FEAC transmitter is sending the all-ones

idle code. It is cleared when the FEAC transmitter is sending a FEAC codeword.

Bit 1: Receive FEAC Codeword Detected (RFCD). This real-time status bit is set each time the FEAC receiver

has detected and validated a new FEAC codeword. It is cleared when the validated codeword is no longer present

on the FEAC channel.

Bit 2: Receive FEAC Idle (RFI). This real-time status bit is set when the FEAC controller has detected 16

consecutive 1s. It is cleared when the FEAC receiver has detected and validated a new FEAC codeword.

Bit 3: Receive FEAC FIFO Empty (RFFE). This real-time status bit is set when the receive FEAC FIFO is empty,

and thus RFF[5:0] contains no valid information. It is cleared when the receive FIFO contains one or more

codewords.

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