AD7651

MASTER SERIAL INTERFACE

Usually, because the AD7651 has a longer acquisition phase than

the conversion phase, the data is read immediately after conversion.

This makes the Master Read After Conversion the most recom-

mended serial mode when it can be used. In this mode, it should be

noted that unlike in other modes, the BUSY signal returns LOW

after the 16 data bits are pulsed out and not at the end of the

conversion phase, which results in a longer BUSY width.

Internal Clock

The AD7651 is configured to generate and provide the serial data

clock SCLK when the EXT/INT pin is held LOW. The AD7651 also

generates a SYNC signal to indicate to the host when the serial data

is valid. The serial clock SCLK and the SYNC signal can be inverted

if desired. Depending on the RDC/SDIN input, the data can be read

after each conversion or during the following conversion. Figure 32

and Figure 33 show detailed timing diagrams of these two modes.

In the Read During Conversion mode, the serial clock and data

toggle at appropriate instants, which minimize potential feed-

through between digital activity and critical conversion decisions

BUSY

SYNC

SCLK

SDOUT

12

3

14

15

16

D15

D14

D2

D1

D0

X

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

02964-0-015

CNVST

CS, RD

EXT/INT = 0

Figure 32. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D15

D14

D2

D1

D0

X

12

3

14

15

16

BUSY

SYNC

SCLK

SDOUT

02964-0-016

CNVST

CS, RD

Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)

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