11/42

M41ST87Y, M41ST87W

Figure 8. Bus Timing Requirements Sequence

Table 2. AC Characteristics

2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.

Symbol

Min

Max

Unit

SCL Clock Frequency

0

400

kHz

Time the bus must be free before a new transmission can start

1.3

µs

M41ST87Y

10

ns

M41ST87W

15

ns

SDA and SCL Fall Time

300

ns

(2)

Data Hold Time

0

µs

START Condition Hold Time

(after this period the first clock pulse is generated)

600

ns

Clock High Period

600

ns

Clock Low Period

1.3

µs

SDA and SCL Rise Time

300

ns

Data Setup Time

100

ns

START Condition Setup Time

(only relevant for a repeated start condition)

600

ns

STOP Condition Setup Time

600

ns

AI00589

SDA

P

tSU:STO

tSU:STA

tHD:STA

SR

SCL

tSU:DAT

tF

tHD:DAT

tR

tHIGH

tLOW

tHD:STA

tBUF

S

P