M5451B7 datasheet(4/12 Pages) STMICROELECTRONICS

4 / 12 page

M5450, M5451

4/12

Table 2. Static Electrical Characteristics

(Tamb within operating range, VDD = 4.75V to 13.2V, VSS = 0V, unless otherwise specified)

Note: 1. Output matching is calculated as the percent variation from I MAX + IMIN/2.

2. With a fixed resistor on the brightness input some variation in brightness will occur from one device to another.

3. Absolute maximum for each output should be limited to 40mA.

4. The VO voltage should be regulated by the user. See Figure 7 and Figure 8 for allowable VO versus IO operation.

Figure 4. Input Data Format

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

VDD

Supply Voltage

.75

13.2

IDD

Supply Current

VDD = 13.2V

7mA

Input Voltage Logical "0" Level

± 10µA Input Bias

- 0.3

0.8

Logical "1" Level

4.75

≤ VDD ≤ 5.25

VDD

VDD > 5.25

VDD - 2

VDD

Brightness Input Current (note 2)

.75

Brightness Input Voltage (pin 19) Input Current = 750µA, Tamb = 25°C

34.3

VO(off)

Off State Out. Voltage

13.

Out. Sink Current (note 3)

Segment OFF

VO = 3V

µA

Segment ON

VO = 1V (note 4)

Brightness In. = 0

µA0

µA

Brightness In. = 100

Brightness In. = 750

µA12

fclock

Input Clock Frequency

0.5

MHz

Output Matching (note 1)

± 20

BIT 34

CLOCK

DATA

LOAD

(INTERNAL)

RESET

(INTERNAL)

START

BIT 1

BIT 35

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