AD7482ASTZ datasheet(16/21 Pages) AD

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AD7482

Rev. B | Page 15 of 20

000...000

ANALOG INPUT

111...111

000...001

000...010

111...110

111...000

011...111

0.5LSB

–OFFSET

+VREF – 1.5LSB

–OFFSET

1LSB = VREF/4096

Figure 22. Transfer Characteristic with Negative Offset

Table 5 shows the expected ADC result for a given analog input

voltage with different offset values and with CLIP tied to logic high.

The combined advantages of the offset and overrange features of

the AD7482 are shown in Table 6. Table 6 shows the same range of

analog input and offset values as Table 5 but with the clipping

feature disabled.

Table 5. Clipping Enabled (CLIP = 1)

Offset VIN

−128

+256

D12

ADC DATA, D[0:11]

−200 mV

1 1 1

−156.25 mV

1 1 0

0 V

256

1 0 0

+78.125 mV

128

384

0 0 0

+2.3431 V

3711

3839

4095

0 0 0

+2.5 V

3967

4095

0 0 1

+2.5775 V

4095

0 1 1

+2.7 V

4095

1 1 1

Table 6. Clipping Disabled (CLIP = 0)

Offset VIN

−128

+256

ADC DATA, D[0:12]

−200 mV

−456

−328

−72

−156.25 mV

−384

−256

0 V

−128

256

+78.125 mV

128

384

+2.3431 V

3711

3839

4095

+2.5 V

3967

4095

4351

+2.5775 V

4095

4223

4479

+2.7 V

4296

4424

4680

If the CLIP input is at logic low, the overrange indicator is disabled

and the AD7482 is able to achieve output codes outside the

nominal 12-bit range of 0 to 4095 (see Figure 6). D12 acts as an

indicator that the ADC is outside this nominal range. If the ADC is

outside this nominal range on the negative side, the ADC outputs a

twos complement code and if the ADC is outside the range on the

positive side, the ADC outputs a straight binary code as normal.

If D12 is Logic 1, D11 indicates if the ADC is out of range on

the positive or negative side. If D11 is Logic 1, the ADC is outside

the nominal range on the negative side and the output code is a

13-bit twos complement number (a negative number). If D11 is

Logic 0, the ADC is outside the nominal range on the positive side

and the output code is a 13-bit straight binary code, see Table 7.

Table 7. DB14, DB13 Decoding, CLIP = 0

DB12

DB11

Output Coding

Straight binary – inside nominal range

Straight binary – outside nominal range

Twos complement – outside nominal range

Values from −327 to +327 can be written to the offset register.

These values correspond to an offset of ±200 mV. A write to the

offset register is performed by writing a 13-bit word to the part

as detailed in the Parallel Interface section. The 10 LSBs of the

13-bit word contain the offset value, whereas the 3 MSBs must

be set to 0. Failure to write 0s to the 3 MSBs may result in the

incorrect operation of the device.

PARALLEL INTERFACE

The AD7482 features two parallel interfacing modes. These

modes are selected by the mode pins (see Table 8).

Table 8. Operating Modes

Operating Mode

Mode 2

Mode 1

Do Not Use

Parallel Mode 1

Parallel Mode 2

Do Not Use

In Parallel Mode 1, the data in the output register is updated on

the rising edge of BUSY at the end of a conversion and is available

for reading almost immediately afterward. Using this mode,

throughput rates of up to 2.5 MSPS can be achieved. This mode

is to be used if the conversion data is required immediately after

the conversion is completed. An example where this may be of use

is if the AD7482 is operating at much lower throughput rates in

conjunction with the nap mode (for power saving reasons), and

the input signal is being compared with set limits within the DSP or

other controller. If the limits are exceeded, the ADC is brought

immediately into full power operation and commences sampling at

full speed. Figure 31 shows a timing diagram for the AD7482

operating in Parallel Mode 1 with both CS and

In Parallel Mode 2, the data in the output register is not updated

until the next falling edge of

RD tied low.

CONVST. This mode can be used

where a single sample delay is not vital to the system operation,

and conversion speeds of greater than 2.5 MSPS are desired. For

example, this may occur in a system where a large amount of

samples are taken at high speed before an FFT is performed for

frequency analysis of the input signal. Figure 32 shows a timing

diagram for the AD7482 operating in Parallel Mode 2 with both

CS and RD tied low.

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