–18–

AD7450

POWER VERSUS THROUGHPUT RATE

By using the power-down mode on the AD7450 when not

converting, the average power consumption of the ADC decreases

at lower throughput rates. Figure 24 shows how, as the throughput

rate is reduced, the device remains in its power-down state longer,

and the average power consumption reduces accordingly. It shows

this for both 5 V and 3 V power supplies.

For example, if the AD7450 is operated in continuous sampling

mode with a throughput rate of 100 kSPS and an SCLK of 18 MHz,

and the device is placed in the power-down mode between

conversions, then the power consumption is calculated as follows:

Power dissipation during normal operation = 9 mW max for

If the power-up time is one dummy cycle, i.e., 1

µs, and the

remaining conversion time is another cycle, i.e., 1

µs, then the

AD7450 can be said to dissipate 9 mW for 2

µs* during each

conversion cycle.

If the throughput rate = 100 kSPS, then the cycle time = 10

µs,

and the average power dissipated during each cycle is:

(2/10)

9 mW = 1.8 mW

during normal operation is 3.75 mW max.

The AD7450 can now be said to dissipate 3.75 mW for 2

µs*

during each conversion cycle.

The average power dissipated during each cycle with a throughput

rate of 100 kSPS is therefore:

(2/10)

3.75 mW = 0.75 mW

This is how the power numbers in Figure 24 are calculated.

For throughput rates above 320 kSPS, it is recommended that the

serial clock frequency is reduced for optimum power performance.

THROUGHPUT – kSPS

100

0.01

0.1

1

10

0

350

100

150

200

50

250

300

SCLK = 15MHz

SCLK = 18MHz

Figure 24. Power vs. Throughput Rate for

Power-Down Mode

MICROPROCESSOR AND DSP INTERFACING

The serial interface on the AD7450 allows the part to be directly

connected to a range of different microprocessors. This section

explains how to interface the AD7450 with some of the more

common microcontroller and DSP serial interface protocols.

AD7450 to ADSP-21xx

The ADSP-21xx DSPs are interfaced directly to the AD7450

without any glue logic required.

The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data-Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 1, Frame Every Word

IRFS = 0

ITFS = 1

To implement the power-down mode, SLEN should be set to

1001 to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 25. The ADSP-21xx

has the TFS and RFS of the SPORT tied together, with TFS

set as an output and RFS set as an input. The DSP operates in

alternate framing mode and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to

CS and, as with all signal processing applica-

tions, equidistant sampling is necessary. However, in this example,

the timer interrupt is used to control the sampling rate of the

ADC and, under certain conditions, equidistant sampling

may not be achieved.

SCLK

SDATA

CS

SCLK

DR

RFS

TFS

AD7450*

ADSP-21xx*

Figure 25. Interfacing to the ADSP-21xx

The timer registers are loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, a value is transmitted with TFS/DT (ADC control word).

The TFS is used to control the RFS and hence the reading of

data. The frequency of the serial clock is set in the SCLKDIV

register. When the instruction to transmit with TFS is given,

(i.e., AX0 = TX0), the state of the SCLK is checked. The DSP

will wait until the SCLK has gone High, Low, and High before

transmission will start. If the timer and SCLK values are chosen

such that the instruction to transmit occurs on or near the rising

edge of SCLK, then the data may be transmitted, or it may wait

until the next clock edge.

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3,

then a SCLK of 2 MHz is obtained and eight master clock

periods will elapse for every 1 SCLK period. If the timer regis-

ters are loaded with the value 803, then 100.5 SCLKs will occur

between interrupts and subsequently between transmit instruc-

tions. This situation will result in nonequidistant sampling as

the transmit instruction is occurring on a SCLK edge. If the

number of SCLKs between interrupts is a whole integer figure of

N, then equidistant sampling will be implemented by the DSP.

*This figure assumes a very small time to enter power-down mode. This will

increase as the burst of clocks used to enter the power-down mode is increased.

Rev. A