REV.

F

–16–

AD7664

PREVIOUS

CONVERSION

CS = 0

CNVST,

RD

BUSY

DATABUS

Figure 15. Slave Parallel Data Timing for Reading

(Read during Convert)

SERIAL INTERFACE

The AD7664 is configured to use the serial interface when the

SER/

PAR is held HIGH. The AD7664 outputs 16 bits of data,

MSB first, on the SDOUT pin. This data is synchronized with

the 16 clock pulses provided on the SCLK pin. The output data

is valid on both the rising and falling edge of the data clock.

MASTER SERIAL INTERFACE

Internal Clock

The AD7664 is configured to generate and provide the serial data

clock SCLK when the EXT/

INT pin is held LOW. The AD7664

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted, if desired. Depending on RDC/SDIN input,

the data can be read after each conversion or during the fol-

lowing conversion. Figures 16 and 17 show the detailed timing

diagrams of these two modes.

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

12

3

14

15

16

D15

D14

D2

D1

D0

X

EXT/

INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

Figure 16. Master Serial Data Timing for Reading (Read after Convert)

EXT/

INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D15

D14

D2

D1

D0

X

12

3

14

15

16

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)