REV. A

AD7677

–17–

SERIAL INTERFACE

The AD7677 is configured to use the serial interface when the

SER/PAR is held high. The AD7677 outputs 16 bits of data,

MSB first, on the SDOUT Pin. This data is synchronized with

the 16 clock pulses provided on the SCLK Pin.

MASTER SERIAL INTERFACE

Internal Clock

The AD7677 is configured to generate and provide the serial

data clock SCLK when the EXT/

INT Pin is held low. The AD7677

also generates a SYNC signal to indicate to the host when the

serial data is valid. The serial clock SCLK and the SYNC signal

can be inverted if desired. The output data is valid on both the

rising and falling edge of the data clock. Depending on RDC/

SDIN input, the data can be read after each conversion, or during

the following conversion.

Figure 17 and Figure 18 show the detailed timing diagrams of

these two modes.

Usually, because the AD7677 is used with a fast throughput, the

mode master, read during conversion, is the most recommended

serial mode when it can be used.

In read-after-conversion mode, unlike in other modes, it should

be noted that the signal BUSY returns low after the 16 data bits

are pulsed out and not at the end of the conversion phase, which

results in a longer BUSY width.

In read-during-conversion mode, the serial clock and data toggle at

appropriate instances minimizes potential feedthrough between

digital activity and the critical conversion decisions.

To accommodate slow digital hosts, the serial clock can be

slowed down by using DIVSCLK.

SLAVE SERIAL INTERFACE

External Clock

The AD7677 is configured to accept an externally supplied serial

data clock on the SCLK pin when the EXT/

INT pin is held

high. In this mode, several methods can be used to read the

data. The external serial clock is gated by

CS and the data are

output when both

CS and RD are low. Thus, depending on CS,

the data can be read after each conversion or during the follow-

ing conversion. The external clock can be either a continuous

or discontinuous clock. A discontinuous clock can be either

CS

SCLK

SDOUT

D15

D14

D1

D0

D13

X15

X14

X13

X1

X0

Y15

Y14

BUSY

SDIN

INVSCLK = 0

X15

X14

X

12

3

14

15

16

17

18

EXT/

INT = 1

RD = 0

Figure 19. Slave Serial Data Timing for Reading (Read After Convert)

CNVST

SDOUT

SCLK

D1

D0

X

D15

D14

D13

12

3

14

15

16

BUSY

INVSCLK = 0

CS

EXT/

INT = 1

RD = 0

Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)