ACE24LA64A

Two-wire Serial EEPROM

VER 1.1

6

Figure 3: Output Acknowledge

Device Addressing

The 64K devices all require an 8-bit device address word following a start condition to enable the chip

for a read or write operation (see to Figure 4).

The device address word consists of a mandatory “1”, “0” sequence for the first four most significant

bits as shown. This is common to all the EEPROM devices.

The next 3 bits are the A2, A1 and A0 device address bits for the 64K EEPROM. These 3 bits must

compare to their corresponding hard-wired input pins.

The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if

this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will

output a “0”. If a compare is not made, the chip

will return to a standby state.

Data Security: The ACE24LA64A has a hardware data protection scheme that allows the user to write

Write Operations

Byte Write:

A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a

“0” and then

clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a

“0”

and the addressing device, such as a microcontroller, must terminate the write sequence with a stop

All inputs are disabled during this write cycle and the EEPROM will not respond until the write is

complete (see to Figure 5).

Page Write:

A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock