AD7888

–12–

CS and the second rising edge of SCLK as shown in Figure 14a.

In microcontroller applications, this is readily achievable by

driving the

CS input from one of the port lines and ensuring

that the serial data read (from the microcontrollers serial port) is

not initiated for 5

µs. In DSP applications, where the CS is

generally derived from the serial frame synchronization line, it is

not possible to separate the first falling edge and second rising

edge of SCLK after the

CS falling edge by up to 5

µs. There-

fore, the user will need to write to the Control Register to exit

this mode and (by writing PM1 = 0 and PM0 = 0) put the part

into normal mode. A second conversion will then need to be

initiated when the part is powered up to obtain a conversion

result as shown in Figure 14b.

SCLK

4 LEADING ZEROES

+ CONVERSION RESULT

CS

DOUT

DATA IN

DIN

1

16

8

4 LEADING ZEROES

+ CONVERSION RESULT

DATA IN

1

16

8

4 LEADING ZEROES

+ CONVERSION RESULT

DATA IN

116

8

PM1 AND PM0 = 0 TO PLACE

THE PART IN NORMAL MODE

PM1 = 1 AND PM0 = 0 TO

PLACE THE PART BACK IN

AUTOSHUTDOWN MODE

CONTROL REGISTER DATA IS LOADED ON

THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 0

THE PART ENTERS

SHUTDOWN AT THE END

OF CONVERSION AS

PM1 = 1 AND PM0 = 0

THE PART REMAINS POWERED

UP AS PM1 AND PM0 = 0

THE PART BEGINS TO POWER-

UP FROM SHUTDOWN

THE PART ENTERS

SHUTDOWN AT THE END OF

CONVERSION AS PM1 = 1

AND PM0 = 0

Figure 14b. Autoshutdown Operation

SCLK

4 LEADING ZEROES + CONVERSION RESULT

CS

DOUT

DATA IN

DIN

CONTROL REGISTER DATA IS LOADED ON

THE FIRST 8 CLOCKS. PM1 = 1 AND PM0 = 1

1

16

4 LEADING ZEROES + CONVERSION RESULT

DATA IN

PM1 = 1 AND PM0 = 1 TO KEEP

THE PART IN THIS MODE

1

16

THE PART POWERS UP

FROM STANDBY ON SCLK

FALLING EDGE AS PM1 = 1

AND PM0 = 1

THE PART ENTERS

STANDBY AT THE END OF

CONVERSION AS

PM1 = 1 AND PM0 = 1

Figure 15. Autostandby Operation

Autostandby (PM1 = 1, PM0 = 1)

In this mode, the AD7888 automatically enters a standby (or

sleep) mode at the end of every conversion. In this standby

mode, all on-chip circuitry, apart from the on-chip reference, is

powered down. This mode is similar to the autoshutdown but

in this case, the power-up time is much shorter as the on-chip

reference remains powered up at all times.

Figure 15 shows the general diagram of the operation of the

AD7888 in this mode. On the first falling SCLK edge after

CS

goes low, the AD7888 comes out of standby. The AD7888

wake-up time is very short in this mode so it is possible to wake

up the part and carry out a valid conversion in the same read/

write operation. The input signal is sampled on the second

rising edge of SCLK following the

CS falling edge. At the end

of conversion (last rising edge of SCLK) the part automatically

enters its standby mode.

REV. C